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Virtex-5 FPGA ML561
Memory Interfaces
Development Board
User Guide
UG199 (v1.2) April 19, 2008
R
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R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any
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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Conventions . . . . . . . . . . . . . . . . . . . . . . . .
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R Seven-Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Light Emitting Diodes (LEDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power On or Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 S
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R Appendix B: Bill of Materials Appendix C: LCD Interface General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Display Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Peripheral Device KS0713 . . . . . . . .
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R 6 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008
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R Preface About This Guide ® This user guide describes the Virtex -5 FPGA ML561 Memory Interfaces Development Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5. Guide Contents This manual contains the following chapters: • Chapter 1, “Introduction” • Chapter 2, “Getting Started” • Chapter 3, “Hardware Description” • Chapter 4, “Electrical Requirements” • Chapter 5, “Signal Integrity Recommendations”
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R Preface: About This Guide - Configurable Logic Blocks (CLBs) -SelectIO™ Resources - SelectIO Logic Resources - Advanced SelectIO Logic Resources • Virtex-5 FPGA RocketIO GTP Transceiver User Guide This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT and SXT platforms. • Virtex-5 FPGA RocketIO GTX Transceiver User Guide This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT platform. ® • Virtex-5 FPGA Embedded Processor Block for PowerPC
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R Conventions Conventions This document uses the following conventions. An example illustrates each convention. Typographical This document uses the following typographical conventions. An example illustrates each convention. Convention Meaning or Use Example See the Virtex-5 Configuration Guide References to other documents for more information. Italic font The address (F) is asserted after Emphasis in text clock event 2. Underlined Text Indicates a link to a web page. http://www.xilinx.com/
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R Preface: About This Guide These measurements are the actual real-time measurements of an eye diagram and a Hardware Measurements segment of the test pattern (PRBS6) waveform captured on ML561 hardware at the designated probe point using an Agilent scope. As the frequency of operation increases, the signal delay is affected by the data pattern that precedes the current data bit. This is called the inter-symbol interference (ISI) effect. All testing is performed with a pseudo-random bitstrea
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R Chapter 1 Introduction ® This chapter introduces the Virtex -5 FPGA ML561 reference design. It contains the following sections: • “About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit” • “Virtex-5 FPGA ML561 Memory Interfaces Development Board” About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit The Virtex-5 FPGA ML561 Memory Interfaces Tool Kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the V
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R Chapter 1: Introduction Virtex-5 FPGA ML561 Memory Interfaces Development Board A high-level functional block diagram of the Virtex-5 FPGA ML561 Memory Interfaces Development Board is shown in Figure 1-1. External Interfaces: System ACE Controller, USB, RS-232, LCD SSTL18/SSTL2 SSTL18 HSTL FPGA #1 FPGA #2 FPGA #3 XC5VLX50T/ XC5VLX50T/ XC5VLX50T/ FFG1136 FFG1136 FFG1136 WIDE UG191_c1_01_020807 DEEP Figure 1-1: Virtex-5 FPGA ML561 Development Board Block Diagram The Virtex-5 FPGA ML561 Devel
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R Virtex-5 FPGA ML561 Memory Interfaces Development Board Figure 1-2 shows the Virtex-5 FPGA ML561 Development Board and indicates the locations of the resident memory devices. 32-bit DDR400 SDRAM 144 bits wide DDR2 SDRAM DIMM 32-bit DDR2 SDRAM 72 bits wide, up to 4 deep 72-bit QDRII SRAM 36-bit RLDRAM II UG199_c1_02_050106 S A i l N 10 t hit / d h d F/L Figure 1-2: Virtex-5 FPGA ML561 Development Board Virtex-5 FPGA ML561 User Guide www.xilinx.com 13 UG199 (v1.2) April 19, 2008
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R Chapter 1: Introduction 14 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2) April 19, 2008
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R Chapter 2 Getting Started This chapter describes the items needed to configure the Virtex-5 FPGA ML561 Memory Interfaces Development Board. The Virtex-5 FPGA ML561 Development Board is tested at the factory after assembly and should be received in working condition. It is set up to load a bitstream from the CompactFlash card at socket J27 through the System ACE controller (U45). This chapter contains the following sections: • “Documentation and Reference Design CD” • “Initial Board Check B
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R Chapter 2: Getting Started 5. Insert the CompactFlash card included in the kit into socket J27 on the Virtex-5 FPGA ML561 Development Board. To select the startup file, check that SW8 is set to position 0. Applying Power to the Board The Virtex-5 FPGA ML561 Development Board is now ready to power on. The Virtex-5 FPGA ML561 Development Board is shipped with a country-specific AC line cord for the universal input 5V desktop power supply. Follow these steps to power up the Virtex-5 FPGA ML5
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R Chapter 3 Hardware Description This chapter describes the major hardware blocks on the Virtex-5 FPGA ML561 Development Board and provides useful design consideration. It contains the following sections: • “Hardware Overview” • “Memory Details” • “External Interfaces” • “Power Regulation” • “Board Design Considerations” Hardware Overview The ML561 Development/Evaluation system reference design is implemented with three XC5VLX50T-FFG1136 devices from the Virtex-5 FPGA family to demonstrate hi
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R Chapter 3: Hardware Description SSTL18 MGT Connections FPGA #1 SSTL2 SPY LEDs A1 V & V TT REF DDR FPGA #2 FPGA #1 DDR SPY FPGA #1 LEDs Test Header 1 FPGA #2 A1 Test Header 2 LEDs MGT DDR2 DDR2 CLK AVC SSTL18 CPLL Config1 V & V TT REF Config2 VVTTR AVTTX AVTRX XC DIP1 12V Banana FBD Clocks & 7SEG2 VCC Jacks DIP2 Buffers External ON V CCINT SSTL2 CLK RS-232 A1 Driver OFF SPY 7SEG1 HSTL Serial Header QDRII V / 12V Input CCAUX RLDRAM II V Jack CCO RESET FPGA #3 12V -> 5V QDRII 5V Banana HSTL RLDRA
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R Hardware Overview Memories Table 3-1 lists the types of memories that the ML561 board supports. Table 3-1: Summary of ML561 Memory Interfaces Data/Strobe Memory Type Maximum Speed Data Rate Data Width I/O Standard Ratios DDR400 SDRAM 200 MHz 400 Mbps 32 SSTL2 8:1 DDR2 DIMM 333 MHz 667 Mbps 144 SSTL18 8:1 DDR2 SDRAM 333 MHz 667 Mbps 32 SSTL18 8:1 QDRII SRAM 300 MHz 1.2 Gbps 72 HSTL18 18:1, 36:1 RLDRAM II 300 MHz 600 Mbps 36 HSTL18 9:1, 18:1 When a larger data/strobe ratio is implemented, for
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R Chapter 3: Hardware Description Wide Deep DQ and DQS BY0-BY7, CB0_7 DQ and DQS BY8-BY15, CB8_15 Address and Commands DIMM1 Control DIMM2 Control DIMM3 Control DIMM4 Control DIMM5 Control UG199_c3_02_050106 Figure 3-2: DDR2 Deep and Wide DIMM Sockets DDR2 SDRAM Components The ML561 board contains two 333 MHz Micron MT47H32M16CC-3 (16-bit) DDR2 SDRAM components that provide a 32-bit interface to FPGA #1. Each 16-bit device is packaged in an 84-ball FBGA package, with a common address and contr
