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87C196CB Supplement to
8XC196NT User’s Manual
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CB_title.fm5 Page 1 Tuesday, September 15, 1998 9:54 AM 87C196CB Supplement to 8XC196NT User’s Manual August 2004 Order Number: 272787-003
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CB_legal.fm5 Page 1 Tuesday, September 15, 1998 9:39 AM Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or w
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 RELATED DOCUMENTS .............................................................................................. 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATURES ..................................................................................................... 2-1 2.2 BLOCK DIAGRAM.......................................
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87C196CB SUPPLEMENT 7.4.4 Programming a Message Acceptance Filter ...........................................................7-17 7.5 CONFIGURING MESSAGE OBJECTS....................................................................... 7-20 7.5.1 Specifying a Message Object’s Configuration .........................................................7-21 7.5.2 Programming the Message Object Identifier ...........................................................7-22 7.5.3 Programming the Message Object
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CONTENTS FIGURES Figure Page 2-1 87C196CB Block Diagram............................................................................................2-2 2-2 Clock Circuitry ..............................................................................................................2-3 2-3 Internal Clock Phases ..................................................................................................2-4 2-4 Effect of Clock Mode on CLKOUT Frequency...........................................
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8XC196CB SUPPLEMENT FIGURES Figure Page A-2 87C196CB 100-pin QFP Package .............................................................................. A-3 vi
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CONTENTS TABLES Table Page 1-1 Related Documents......................................................................................................1-2 2-1 Features of the 8XC196NT and 87C196CB.................................................................2-1 2-2 State Times at Various Frequencies ............................................................................2-4 2-3 Relationships Between Input Frequency, Clock Multiplier, and State Times ...............2-5 3-1 Register File Mem
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1 Guide to This Manual
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CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196NT Microcontroller User’s Manual. It describes the differences between the 87C196CB and the 8XC196NT. For information not found in this supplement, please consult the 8XC196NT Microcontroller User’s Manual (order number 272317) or the 87C196CB datasheet (87C196CA/87C196CB 20 MHz Advanced 16-Bit CHMOS Microcontroller with Integrated CAN 2.0, order number 272405). 1.1 MANUAL CONTENTS This supplement contains several chapters
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87C196CB SUPPLEMENT Chapter 9 — Interfacing with External Memory — discusses differences in the bus timing modes supported by the 8XC196NT and the 87C196CB. Chapter 10 — Programming the Nonvolatile Memory — describes the memory maps and rec- ommended circuits to support programming of the 87C196CB’s 56 Kbytes of OTPROM. Appendix A — Signal Descriptions — describes the additional signals implemented on the 87C196CB. Glossary — defines terms with special meaning used throughout this supplement. In
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2 Architectural Overview
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CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural differences between the 87C196CB and the 8XC196NT. Both the 8XC196NT and the 87C196CB are designed for high-speed calculations and fast I/O. With the addition of the CAN (controller area network) peripheral, the 87C196CB reduces point- to-point wiring requirements, making it well-suited to automotive and factory automation appli- cations. The 87C196CB is available in either an 84-pin or a 100-pin package. The 84-pin 87C196CB,
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87C196CB SUPPLEMENT 2.2 BLOCK DIAGRAM Figure 2-1 shows the major blocks within the device. The 8XC196NT and 87C196CB have the same peripheral set with the exception of the CAN (controller area network) peripheral, which is unique to the 87C196CB. The CAN peripheral manages communications between multiple net- work nodes. This integrated peripheral is similar to Intel’s standalone 82527 CAN serial commu- nications controller, supporting both the standard and extended message frames specified by t
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ARCHITECTURAL OVERVIEW Disable PLL (Powerdown) F XTAL1 Phase XTAL1 Filter Comparator Phase- locked XTAL2 Oscillator Disable Clock Input Disable Phase-locked Loop (Powerdown) Oscillator Clock Multiplier (Powerdown) f Divide-by-two Circuit f Disable Clocks PLLEN 2 (Powerdown) Peripheral Clocks (PH1, PH2) Clock CLKOUT Generators CPU Clocks (PH1, PH2) Disable Clocks (Idle, Powerdown) A3168-01 Figure 2-2. Clock Circuitry The rising edges of PH1 and PH2 generate the internal CLKOUT si
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87C196CB SUPPLEMENT XTAL1 tt 1 State Time 1 State Time PH1 PH2 CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0805-01 Figure 2-3. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2. State Times at Various Frequencies f (Frequency Input to the State Time Divide-by-two Circuit) 8 MHz 250 ns 12 MHz 167 ns 16 MHz 125 ns 20 MHz 10
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ARCHITECTURAL OVERVIEW PLLEN = 0 XTAL1 (5 MHz) t = 80ns f T XHCH CLKOUT PLLEN = 1 XTAL1 (5 MHz) t = 20ns f T XHCH CLKOUT A3170-01 Figure 2-4. Effect of Clock Mode on CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times F f t XTAL1 (Frequency PLLEN Multiplier (Input Frequency to (Clock State Time on XTAL1) the Divide-by-two Circuit) Period) 4 MHz 0 1 4 MHz 250 ns 500 ns 5 MHz 0 1 5 MHz 200 ns 400 ns 8 MHz 0 1 8 MHz 125 ns 250 ns 12 MHz 0 1 12
