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CY7C1370DV25
CY7C1372DV25
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
• Pin-compatible and functionally equivalent to ZBT™ The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
• Supports 250-MHz bus operations with zero wait states
No Bus Latency™ (NoBL™) logic, respectively. They are
— Available speed grades are 250, 200 and 167 MHz
designed to support unlimited true back-to-back Rea
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CY7C1370DV25 CY7C1372DV25 Logic Block Diagram-CY7C1372DV25 (1M x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U A ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BWa WRITE E DQs U ARRAY S CONTROL LOGIC G DRIVERS A F T DQPa I M E F BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Contro
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CY7C1370DV25 CY7C1372DV25 Pin Configurations 100-Pin TQFP Pinout DQPc 1 NC DQPb 1 A 80 80 DQc 2 NC DQb 2 NC 79 79 DQc 3 DQb NC 3 NC 78 78 V V DDQ 4 V DDQ 4 77 V DDQ 77 DDQ V 5 V V SS 5 V 76 SS SS 76 SS DQc 6 NC DQb 6 NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V SS V 10 V SS 10 V 71 SS 71 SS V V DDQ DDQ 11 V 11 70 DDQ V 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS CY7C1370DV25 67 SS V DD V 15 NC DD 15 NC 6
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CY7C1370DV25 CY7C1372DV25 Pin Configurations (continued) 119-Ball BGA Pinout CY7C1370DV25 (512K × 36) 1 23 4 5 6 7 A V AAAV A A DDQ DDQ B NC/576M CE A ADV/LD ACE NC 2 3 C NC/1G A A V AA NC DD D DQ DQP V NC V DQP DQ c c SS SS b b DQ DQ V CE V DQ DQ E c c SS 1 SS b b F V DQ V V DQ V OE DDQ c SS SS b DDQ DQ DQ A DQ DQ G BW BW c c b b c b DQ DQ V DQ DQ H V c c SS WE b b SS V V NC V NC V V J DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ d d SS SS a a L DQ DQ NC DQ DQ BW BW d d a a d a M V DQ V V DQ V CEN
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CY7C1370DV25 CY7C1372DV25 Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1370DV25 (512K × 36) 1 2 3 4 567 89 10 11 A NC/576M A ADV/LD A A NC CE BW BW CE CEN 1 c b 3 B NC/1G A CE2 CLK WE OE A A NC BW BW d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS SS SS DDQ b DQ DQ V V V V V V V DQ DQ D c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ E c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ G c c DDQ DD SS SS S
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CY7C1370DV25 CY7C1372DV25 Pin Definitions Pin Name I/O Type Pin Description A0 Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of A1 Synchronous the CLK. A BW Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. a BW Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , b a a a b b b BW BW controls DQ and DQP , BW controls DQ and DQP . c c c c d d d BW d WE Input
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CY7C1370DV25 CY7C1372DV25 Pin Definitions (continued) Pin Name I/O Type Pin Description V Power Supply Power supply inputs to the core of the device. DD V I/O Power Power supply for the I/O circuitry. DDQ Supply V Ground Ground for the device. Should be connected to ground of the system. SS NC – No connects. This pin is not connected to the die. NC/(36M, 72M, – These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 144M, 288M, 576M, and 1G densities. 576M,
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CY7C1370DV25 CY7C1372DV25 signals. The CY7C1370DV25/CY7C1372DV25 provides byte Sleep Mode write capability that is described in the Write Cycle Description The ZZ input pin is an asynchronous input. Asserting ZZ table. Asserting the Write Enable input (WE) with the selected places the SRAM in a power conservation “sleep” mode. Two Byte Write Select (BW) input will selectively write to only the clock cycles are required to enter into or exit from this “sleep” desired bytes. Bytes not selected d
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CY7C1370DV25 CY7C1372DV25 [1, 2, 3, 4, 5, 6, 7] Truth Table Address Operation Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Deselect Cycle None H L L X X X L L-H Tri-state Continue Deselect Cycle None X L H X X X L L-H Tri-state Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-state Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-state Write Cycle (Begin
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CY7C1370DV25 CY7C1372DV25 Function (CY7C1372DV25) WE BW BW b a Read H x x Write – No Bytes Written L H H Write Byte a – (DQ and DQP)LHL a a Write Byte b – (DQ and DQP)LLH b b Write Both Bytes L L L Test Mode Select (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1370DV25/CY7C1372DV25 incorporates a serial and is sampled on the rising edge of TCK. It is allowable to boundary scan test access port (TAP).This part is fully leave
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CY7C1370DV25 CY7C1372DV25 TAP Registers through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP Registers are connected between the TDI and TDO balls and controller needs to be moved into the Update-IR state. allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through EXTEST the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Dat
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CY7C1370DV25 CY7C1372DV25 BYPASS current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place When the BYPASS instruction is loaded in the instruction the output bus into a High-Z condition. register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The This bit can be set by entering the SAMPLE/PRELOAD or advantage of the BYPASS instruction is that it shortens the EXTEST command,
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CY7C1370DV25 CY7C1372DV25 [9, 10] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Set-up Times t TMS Set-up to TCK Clock Rise 5 ns TMSS t TDI Set-up to TCK Clock Rise 5 ns TDIS t Capture Set-up to TCK Rise 5 ns CS Hold Times
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CY7C1370DV25 CY7C1372DV25 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent 1.25V Input pulse levels ................................................ V to 2.5V SS Input rise and fall time..................................................... 1 ns 50Ω Input timing reference levels.........................................1.25V Output reference levels.................................................1.25V TDO Test load termination supply voltage.............................1.25V Z = 5
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CY7C1370DV25 CY7C1372DV25 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a Hig
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CY7C1370DV25 CY7C1372DV25 [12, 14] 165-Ball FBGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N6 31 D10 61 G1 2N7 32 C11 62 D2 3N10 33 A11 63 E2 4P11 34 B11 64 F2 5P8 35 A10 65 G2 6R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9
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CY7C1370DV25 CY7C1372DV25 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current..................................
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CY7C1370DV25 CY7C1372DV25 [17] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit C Input Capacitance T = 25°C, f = 1 MHz, 5 8 9 pF IN A V = 2.5V. DD C Clock Input Capacitance 5 8 9 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 8 9 pF I/O [17] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 28.66 23.8 20.7 °C/W JA (Juncti
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CY7C1370DV25 CY7C1372DV25 [22, 23] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max. Min. Max. Min. Max. Unit [18] t V (typical) to the first access read or write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5 6 ns CYC F Maximum Operating Frequency 250 200 167 MHz MAX t Clock HIGH 1.7 2.0 2.2 ns CH t Clock LOW 1.7 2.0 2.2 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.0 3.4 ns CO t OE LOW to Output Valid 2.6 3.0 3.4 ns EOV t Data
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CY7C1370DV25 CY7C1372DV25 Switching Waveforms [24, 25, 26] Read/Write/Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BWx A1 A2 A3 A4 A5 A6 A7 ADDRESS t CO t t DS DH t t t t DOH CLZ OEV CHZ t t AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: 24. For thi
