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CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18
• Available speed grades are 250, 200, and 167 MHz
SRAM cells with advanced synchronous peripheral circuitry
• Registered inputs and outputs for pipelined operation
and a two-bit counter for internal burst operation. All
•
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 [3] Logic Block Diagram – CY7C1386DV25/CY7C1386FV25 (512K x 36) ADDRESS A0,A1,A REGISTER 2 A[1:0] MODE Q1 ADV BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ D,DQP D DQ D,DQP D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ c,DQP C DQ c,DQP C MEMORY BYTE BYTE BW C ARRAY OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER SENSE DQs BUFFERS REGISTERS AMPS DQP A DQ B,DQP B E DQ B,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQ A,DQP
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Pin Configurations 100-pin TQFP Pinout (3 Chip Enables) DQP C DQP 1 80 NC B 1 80 A DQ C DQ 2 79 NC B 2 79 NC DQ C DQ 3 78 NC B 3 78 NC V DDQ 4 77 V DDQ V DDQ 4 77 V DDQ V SSQ 5 76 V SSQ V SSQ V 5 76 SSQ DQ C 6 75 DQ B NC NC 6 75 DQ C 7 74 DQ B NC DQP 7 74 A DQ C 8 73 DQ B DQ B DQ 8 73 A DQ C DQ 9 72 B DQ B DQ 9 72 A V SSQ V 10 71 V SSQ SSQ 10 71 V SSQ V DDQ V 11 70 V DDQ DDQ 11 70 V DDQ DQ C DQ 12 69 DQ B B 12 69 DQ A DQ C DQ 13 68 DQ B B 1
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Pin Configurations (continued) 119-Ball BGA (1 Chip Enable) CY7C1386FV25 (512K x 36) 1 23 4 5 6 7 A V AA A A V DDQ ADSP DDQ A B NC/288M A ADSC A A NC/576M C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V CE V DQ DQ C C SS 1 SS B B F V DQ V V DQ V OE DDQ C SS SS B DDQ G DQ DQ BW BW DQ DQ ADV C C C B B B H DQ DQ V V DQ DQ C C SS GW SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386DV25 (512K x 36) 1 23 4 5 6 7 89 10 11 A NC/288M A NC A CE BW BW CE BWE ADSC ADV 1 C B 3 B NC/144M A CE BW BW CLK A NC/576M GW OE ADSP 2 D A DQP NC V V V V V V V NC/1G DQP C C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C C DDQ DD SS SS SS
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Pin Definitions Name IO Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the 0 1 [2] Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE 1 2 3 are sampled active. A1: A0 are fed to the two-bit counter. . BW , BW Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes A B BW , BW Synchronous to the SRAM. Sampled on the rising e
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Pin Definitions (continued) Name IO Description V Ground Ground for the core of the device. SS V IO Ground Ground for the IO circuitry. SSQ V IO Power Supply Power supply for the IO circuitry. DDQ MODE Input- Selects burst order. When tied to GND selects linear burst sequence. When tied Static to V or left floating selects interleaved burst sequence. This is a strap pin and DD must remain static during device operation. Mode pin has an int
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 The write signals (GW, BWE, and ) and ADV inputs are Burst Sequences BW X ignored during this first cycle. The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 provides a two-bit wraparound counter, fed ADSP triggered write accesses require two clock cycles to by A , that implements either an interleaved or linear burst complete. If GW is asserted LOW on the second clock rise, the [1:0] sequence. The interleaved burst sequence is designe
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V 80 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ Active to sleep current This parameter is sampled 2t ns ZZI CYC t ZZ Inactive to exit sleep current This parameter is sampled 0 ns RZZI [4, 5, 6, 7, 8, 9] Truth Table Operation Add. Used CE CE C
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 [5, 10] Partial Truth Table for Read/Write Function (CY7C1386DV25/CY7C1386FV25) GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – (DQ and DQP) H L HHH L A A Write Byte B – (DQ and DQP)H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP) H LH LH H C C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQ and DQP) H L L HHH D D Write Bytes D, A H L L
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 unconnected if the TAP is not used. The ball is pulled up IEEE 1149.1 Serial Boundary Scan (JTAG) internally, resulting in a logic HIGH level. The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ Test Data-In (TDI) CY7C1387FV25 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The The TDI ball is used to serially input information into the TAP operates using JEDEC-standard 3.3V or 2.5V IO logic regist
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Instruction Register To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the EXTEST TDI and TDO balls as shown in the TAP Controller Block The EXTEST instruction enables the preloaded data to be Diagram. Upon power up, the instruction register is loaded driv
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 The shifting of data for the SAMPLE and PRELOAD phases the TAP controller, it will directly control the state of the output can occur concurrently when required; that is, while data (Q-bus) pins, when the EXTEST is entered as the current captured is shifted out, the preloaded data can be shifted in. instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output BYPASS bus into a Hig
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 TAP AC Switching Characteristics [11, 12] Over the Operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TC
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Identification Register Definitions CY7C1386DV25/ CY7C1387DV25/ Instruction Field Description CY7C1386FV25 CY7C1387FV25 Revision Number (31:29) 000 000 Describes the version number. Device Depth (28:24) 01011 01011 Reserved for internal use Device Width (23:18) 119-BGA 101110 101110 Defines the memory type and architecture. Device Width (23:18) 165-FBGA 000110 000110 Defines the memory type and architecture. Cypress Device ID (17:12) 100101
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 [14, 15] 119-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 23 F6 45 G4 67 L1 H4 2 T4 24 E746 A468 M2 3T5 25 D7 47 G3 69 N1 4 T6 26 H748 C370 P1 5R5 27 G6 49 B2 71 K1 6 L5 28 E650 B372 L2 7R6 29 D6 51 A3 73 N2 8 U6 30 C752 C274 P2 9 R7 31 B753 A275 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 [14, 16] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N6 31 D10 61 G1 2N7 32 C11 62 D2 3N10 33 A11 63 E2 4P11 34 B11 64 F2 5P8 35 A10 65 G2 6R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage........................................... >2001V the device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C La
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 [19] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package C Input Capacitance T = 25°C, f = 1 MHz, 5 8 9 pF IN A V /V = 2.5V DD DDQ C Clock Input Capacitance 5 8 9 pF CLK C Input/Output Capacitance 5 8 9 pF IO [19] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package Θ Thermal Resistance Test conditions follow standard 28.66 23.8
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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Switching Characteristics [20, 21] Over the Operating Range 250 MHz 200 MHz 167 MHz Parameter Description Unit Min. Max. Min. Max. Min. Max. [22] t V (Typical) to the first Access 1 11 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC t Clock HIGH 1.7 2.0 2.2 ns CH t Clock LOW 1.7 2.0 2.2 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.0 3.4 ns CO t Data Output Hold After CLK Rise 1.0 1.3 1.3 ns DOH [23, 24, 25] t Clock to
