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®
Intel IXD1110 Demo Board
Development Kit Manual
June 2003
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
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® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents Contents 1.0 Introduction.........................................................................................................................7 1.1 About This Kit.....................................................................................................................7 1.2 Additional Equipment Required..........................................................................................7 1.3 About This Demo Board .......................................................
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Contents Figures ® 1Intel IXD1110 Demo Board (Top View)...............................................................9 2 Typical Test Setup .............................................................................................12 ® 3Intel IXF1110 CPU Daughter Card....................................................................13 ® 4Intel IXD1110 Demo Board Power (Revision A1) .............................................25 ® 5Intel IXD1110 Digital Power ...............................
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Contents Revision History Revision 003 Rev. Date: June 27, 2003 Page # Description 11 Added second bullet under Section 2.0, “Quick Start”. ® 13 Modified Figure 3, “Intel IXF1110 CPU Daughter Card”. 16 Added Section 5.3, “Changing the IP Address of the CPU Daughter Card (Optional)”. 18 Added note under Section 6.2, “JTAG Test Signals”. 18 Modified pin 8 description in Table 3, “JTAG Test Signals (JP1)”. 19 Modified Table 4, “IXF1110 LED Behavior”. Revision Number: 002 Revision Date: July 31, 200
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Contents 6 Development Kit Manual Document Number: 250807 Revision Number: 003 Revision Date: June 27, 2003
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IXD1110 Demo Board 1.0 Introduction This document describes all the necessary requirements, settings, and procedures for evaluating the ® Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (MAC) using the ® Intel IXD1110 demo board. For immediate operation, refer to Section 2.0, “Quick Start” on page 11. For optional configurations, see Section 6.0, “Optional Configurations” on page 18. The IXD1110 demo board kit includes a CPU daughter card that attaches to the underside of th
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IXD1110 Demo Board 1.3 About The IXD1110 Demo Board The IXD1110 demo board provides a working platform for the evaluation of the IXF1110 in 1000 Mbps fiber optic applications. All ten network ports provide a 1000BASE-SX connection through the GBIC Small Form Factor Pluggable (SFP) modules (not included). The IXD1110 demo board contains one IXF1110 device, one SPI4-2 interface connector, ten GBIC SFP connectors, and one plug-in CPU daughter card. The SPI4-2 interface connector allows for loop
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IXD1110 Demo Board 1.3.2 Component Location and Description Figure 1 illustrates the top view of the IXD1110 demo board. ® Figure 1. Intel IXD1110 Demo Board (Top View) GBIC SFP GND 1.8GND V IXF 2.5 V IXF 3.3 V 2.5 V Connectors Port 0 Port 1 Port 2 EPROM Port 3 SMB Connectors Mictor Connector Probe D Port 4 FPGA JP1 ® Intel SPI4-2 J T Connector IXF1110 A G Mictor Connector Port 5 Probe C Mictor Connector Port 6 Probe A Port 7 Reset JP2 Port 8 S1 ® Intel IXF1110 Port 9 LEDs Table 1 provides a lis
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IXD1110 Demo Board ® Table 1. Intel IXD1110 Demo Board Principal Components (Continued) Component Description S1 Reset Switch: This switch resets the entire board when pressed. SPI4-2 Interface Allows a loopback connection when the loopback module is installed. This connector Connector can also interface with alternate SPI4-2 connections. Mictor Connectors A, Provide access to selected IXF1110 signals. Refer to Section 8.4, “Mictor Connectors” 1 C, and D on page 21 for more information. GBIC C
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IXD1110 Demo Board 2.0 Quick Start The quick-start procedure allows for IXF1110 1000 Mbps SerDes data transfer evaluation in the following interfaces: • IXF1110 SPI4-2 loopback data transfer 2 • I C signals • CPU interface 2.1 Setup The following quick-start procedure uses the IXIA* 1600T packet generator to evaluate the IXD1110 demo board. All ports on the IXF1110 are set to a default setting of 1000 Mbps full-duplex (see Figure 2, “Typical Test Setup” on page 12). 1. Set reset jumper JP2 to
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IXD1110 Demo Board 3.0 Typical Test Setup Figure 2 shows a typical test setup for standard operation of the IXF1110 (see Section 2.0, “Quick Start” on page 11 for step-by-step details). The IXD1110 demo board can be connected to an IXIA* 1600T packet generator with LM1000SX cards for evaluation of the board. Each port can be connected to the IXIA* box with fiber cables. For IXF1110 software use, connect CAT5-UTP cables to the ports shown on the CPU daughter card. One of the cables connects t
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IXD1110 Demo Board 4.0 CPU Daughter Card The IXD1110 demo board uses the Embedded Planet* RPX Classic LF (CLLF_BW31), a single- board computer that uses the Motorola* MPC860 CPU. This card attaches to the underside of the board and is used to interface with the IXF1110 CPU interface. Figure 3 provides a top-level view of the CPU daughter card. ® Figure 3. Intel IXF1110 CPU Daughter Card CPU Daughter Card IP Address located on the side of the connector RJ-45 #1 10Mbps Not Used Ethernet Connecti
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IXD1110 Demo Board For more information on the HyperTerminal and GUI interfaces, please refer to the IXF1110 Software Help File. 4.1 CPU FPGA The IXD1110 demo board has a Field Programmable Gate Array (FPGA) that allows the Motorola* CPU, which requires a synchronous interface, to interoperate with the asynchronous IXF1110 CPU interface. For additional information regarding the IXF1110 CPU interface, refer to the IXF1110 Datasheet. 4.2 IXF1110 Register Modifications on Startup The Motorola*
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IXD1110 Demo Board 5.0 IXF1110 Software The IXF1110 software allows access to the following register blocks through the Graphical User Interface (GUI) or the Serial Monitor (HyperTerminal) interface: • MAC Control • MAC RX Statistics • MAC TX Statistics • Global Status and Configuration • RX Block • TX Block • SPI4-2 Block • SerDes Block • GBIC Block For additional information on all of the registers, please refer to the IXF1110 Datasheet or On-Line Help. Note: For help on using IXF1110 softw
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IXD1110 Demo Board 5.2 Installing the IXF1110 Software For proper installation of the IXF1110 software, follow these steps: 1. Verify that the CAT5-UTP cable is connected between the PC and the IXF1110 CPU daughter card. This allows access to the GUI interface. Refer to Section 4.0, “CPU Daughter Card” on page 13 for detailed installation instructions. 2. (Optional) The following connection is required to access the HyperTerminal interface: — CAT5-UTP cable (connected to a CPU daughter card) —
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IXD1110 Demo Board • Parity: None • Stops bits: 1 • Flow Control: None 3. Press the reset button switch SW1. The following message appears on the HyperTerminal: MPC8xx PlanetCore Boot Loader v2.00 Copyright 2001 Embedded Planet. All rights reserved. DRAM available size = 16 MB wvCV DRAM OK Autoboot in 2 seconds. ESC to abort, SPACE or ENTER to go. 4. Press the ESC key to stop the Autoboot. The following message appears on the HyperTerminal: Autoboot aborted. > 5. Type the following at the > pro
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IXD1110 Demo Board 6.0 Optional Configurations 6.1 Reset Jumper JP2 6.1.1 Standard Operation The Reset Jumper JP2 is required for standard operation of the IXD1110 demo board. Use the HRESET position for standard operation. The POR position is not recommended for standard operation of the IXD1110 demo board. This configuration only affects the CPU operation, and does not affect IXF1110 operation. The only difference between HRESET and POR is that POR also resets the CPU PLLs and state machine
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IXD1110 Demo Board 7.0 LEDs Table 4 describes the behavior of the Link LED - Amber, Link LED - Green, and Activity LED for the IXF1110. Table 4. IXF1110 LED Behavior Type Status Description Synchronization has occurred but no packets are being Off received and the Link LED Enable Register (Addr: 0x502) is not set. RX Synchronization has not occurred or no optical Amber On signal exists. Port has remote fault and the LED Fault Disable RxLED Amber Blinking Register (Addr: 0x50B) is not set. B
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IXD1110 Demo Board 8.0 Test Points 8.1 Reset Test Points Two test points allow evaluation of the IXF1110 reset signals. TP21 allows IXF1110 Sys_Res signal monitoring. DTP3 allows board reset signal monitoring. The board Sys_Res can be monitored on both test points if it is asserted by Switch S1 or the CPU. The reset is seen at TP21 if an IXF1110 reset is issued by the software interface. ® Table 5. Intel IXF1110 Reset Test Points IXF1110 Ball Test Point Symbol Description Designator TP21 Sys
