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®
Desktop 4th Generation Intel
Core™ Processor Family, Desktop
® ®
Intel Pentium Processor
®
Family, and Desktop Intel
®
Celeron Processor Family
Specification Update
December 2013
Revision 007
Reference Number: 328899-007
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, ME
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Contents Contents Revision History...............................................................................................................5 Preface ..............................................................................................................................6 Summary Tables of Changes..........................................................................................8 Identification Information .......................................................................
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Contents 4 Specification Update
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Revision History Revision Description Date 001 • Initial Release. June 2013 • No Updates. Revision number added to Revision History to maintain 002 N/A consistency with NDA Specification Update numbering. •Errata 003 — Added HSD59-99 August 2013 • Updated Identification Information • No Updates. Revision number added to Revision History to maintain 004 N/A consistency with NDA Specification Update numbering. •Errata — Moved previous HSD99 to HSD108 005 November 2013 — Added HSD99-107 and HS
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Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also co
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Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor iden
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Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations. Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated. Specification Change
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Errata (Sheet 1 of 5) Steppings Number Status ERRATA C-0 LBR, BTS, BTM May Report a Wrong Address when an Exception/ HSD1 XNo Fix Interrupt Occurs in 64-bit Mode EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after HSD2 XNo Fix a Translation Change MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a HSD3 XNo Fix DTLB Error HSD4 XNo Fix LER MSRs May Be Unreliable MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in HSD5 XNo Fix Hang An Uncorre
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Errata (Sheet 2 of 5) Steppings Number Status ERRATA C-0 Specific Graphics Blitter Instructions May Result in Unpredictable HSD26 XNo Fix Graphics Controller Behavior Processor May Enter Shutdown Unexpectedly on a Second HSD27 XNo Fix Uncorrectable Error Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates Do HSD28 XNo Fix Not Follow PCIe* Specification HSD29 XNo Fix Performance Monitor Counters May Produce Incorrect Results HSD30 XNo Fix Performance Monitor UOPS_EXECUTED Even
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Errata (Sheet 3 of 5) Steppings Number Status ERRATA C-0 Internal Parity Errors May Incorrectly Report Overflow in The HSD55 XNo Fix IA32_MCi_STATUS MSR Performance Monitor Events OTHER_ASSISTS.AVX_TO_SSE And HSD56 XNo Fix OTHER_ASSISTS.SSE_TO_AVX May Over Count HSD57 XNo Fix Processor May Run at Incorrect P-State Performance Monitor Event DSB2MITE_SWITCHES.COUNT May Over HSD58 XNo Fix Count Performance Monitor Register UNC_PERF_GLOBAL_STATUS Not HSD59 XNo Fix Restored on Package C7 Exit
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Errata (Sheet 4 of 5) Steppings Number Status ERRATA C-0 HSD82 XNo Fix PCIe* Host Bridge DID May Be Incorrect HSD83 XNo Fix Transactional Abort May Produce an Incorrect Branch Record SMRAM State-Save Area Above the 4GB Boundary May Cause HSD84 XNo Fix Unpredictable System Behavior DMA Remapping Faults for the Graphics VT-d Unit May Not Properly HSD85 XNo Fix Report Type of Faulted Request AVX Gather Instructions Page Faults May Report an Incorrect Faulting HSD86 XNo Fix Address HSD87 XNo Fix
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Errata (Sheet 5 of 5) Steppings Number Status ERRATA C-0 A PEBS Record May Contain Processor State for an Unexpected HSD110 XNo Fix Instruction HSD111 XNo Fix MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data x87 FPU DP May be Incorrect After Instructions That Save FP State to HSD112 XNo Fix Memory HSD113 XNo Fix Processor May Hang During Package C7 Exit HSD114 XNo Fix Intel® TSX Instructions May Cause Unpredictable System behavior HSD115 XNo Fix Spurious LLC Machine Check May Occur HSD11
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Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents. ® Table 1. Desktop 4th Generation Intel Core™ Processor Family Component Identification Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number ID 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0011b 00b 0110b 1100b xxxxb Notes: 1. The Extended Family, Bits [27:20] are used in conjunction with
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Component Marking Information The processor stepping can be identified by the following component markings. ® Figure 1. Desktop 4th Generation Intel Core™ Processor Family Top-Side Markings Table 2. Desktop Processor Identification (Sheet 1 of 2) Max Thermal Cache Func- Integrated Turbo Core S-Spec Processor Memory Design Stepping Size tional Graphics Freq. Freq. Number Number (MHz) Power (MB) Core Cores Rate (GHz) (W) (GHz) SR147 I7-4770K C-0 8 4 2 3.9 1600 3.5 95 SR149 I7-4770 C-0 8 4
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Table 2. Desktop Processor Identification (Sheet 2 of 2) Max Thermal Cache Func- Integrated Turbo Core S-Spec Processor Memory Design Stepping Size tional Graphics Freq. Freq. Number Number (MHz) Power (MB) Core Cores Rate (GHz) (W) (GHz) SR18K I7-4770R C-0 6 4 3 3.9 1600 3.2 65 SR18M I5-4670R C-0 4 4 3 3.7 1600 3 65 SR18Q I5-4570R C-0 4 4 3 3.2 1600 2.7 65 SR1BW I7-4771 C-0 8 4 2 3.9 1600 3.5 95 SR1CA I5-4570T C-0 4 2 2 3.6 1600 2.9 35 SR1CE G3430 C-0 3 2 1 3.3 1600 3.3 65 SR1CG G3220 C-0
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Errata HSD1. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will s
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HSD4. LER MSRs May Be Unreliable Problem: Due to certain internal processor events, updates to the LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when no update was expected. Implication: The values of the LER MSRs may be unreliable. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. HSD5. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang Problem: If the target linear address r
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HSD8. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM Problem: In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode). Due to this erratum, if 1. A performance counter overflowed before an SMI 2. A PEBS record has not yet been generated because another count of the ev
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HSD11. Performance Monitor Precise Instruction Retired Event May Present Wrong Indications Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated (INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1 programmed in PEBS mode), the processor may return wrong PEBS/PMI interrupts and/or incorrect counter values if the counter is reset with a SAV below 100 (Sample-After-Value is the counter reset value software programs in MSR IA32_PMC1[47:0] in orde
