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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
■ Pin-compatible and functionally equivalent to ZBT™
are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
■ Supports 250 MHz bus operations with zero wait states
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back read
❐ Available spee
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Logic Block Diagram – CY7C1470BV33 (2M x 36) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U T E T A P N P U T U S T ADV/LD A T E WRITE REGISTRY R MEMORY AND DATA COHERENCY WRITE E S B DQ s BW a ARRAY CONTROL LOGIC G U DRIVERS A T DQ Pa BW b I F BW c E DQ Pb M S F BW d T E DQ Pc E P E R R DQ Pd S WE R S I S E N E G INPUT INPUT E E REGISTER 1 REGISTER 0
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Logic Block Diagram – CY7C1474BV33 (1M x 72) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U ADV/LD A T N T T WRITE REGISTRY S BW a A R MEMORY E B AND DATA COHERENCY WRITE E DQ s BW b U ARRAY S CONTROL LOGIC G BW c DRIVERS A T F DQ Pa I M F E BW d S DQ Pb P E E T S R R DQ Pc BW e E I S R BW f DQ Pd N S G BW g DQ Pe E E BW h DQ Pf DQ Pg DQ
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Pin Configurations Figure 1. 100-Pin TQFP Pinout DQPc 1 NC DQPb 1 A 80 80 DQc 2 NC DQb 2 NC 79 79 DQc 3 DQb NC 3 NC 78 78 V DDQ 4 V DDQ 4 V 77 DDQ V 77 DDQ V 5 V SS V 5 V 76 SS SS 76 SS DQc 6 NC 6 NC 75 DQb 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS 10 SS V 71 SS 71 V V DDQ 11 DDQ V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS 67 SS V DD V 15 NC
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470BV33 (2M x 36) 1 23 4 5 6 7 89 10 11 NC/576M A A A NC A CE ADV/LD CE BW BW CEN 3 1 c b NC/1G A CE2 CLK WE OE A A NC B BW BW d a C DQP NC V V V V V V V NC DQP c DDQ SS SS SS SS SS DDQ b D DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b E DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474BV33 (1M × 72) 12 3 4 5 6 7 8 9 10 11 A DQg DQgAA CE ADV/LDA CEA DQb DQb 2 3 B DQg DQg BWS BWS NC WE A BWS BWS DQb DQb c g b f C DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb h d 1 e a D DQg NC DQg V NC/1G OE NC NC V SS DQb SS DQb E DQPg DQPc V V V V V V V DDQ DDQ DDQ DDQ DD DD DD DQPf DQPb F DQc DQc V V V DQf V V NC V SS SS SS SS SS SS DQf G DQc V DQc V V V V NC DD V DDQ DDQ
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Table 1. Pin Definitions Pin Name IO Type Pin Description A0 Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge A1 Synchronous of the CLK. A BW Input- Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. a BW Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , b a a a b b b BW BW controls DQ and DQP , BW controls DQ and DQP , BW co
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Table 1. Pin Definitions (continued) Pin Name IO Type Pin Description TMS Test Mode Select This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG Clock Clock Input to the JTAG Circuitry. Power Supply Power Supply Inputs to the Core of the Device. V DD IO Power Supply Power Supply for the IO Circuitry. V DDQ Ground Ground for the Device. Should be connected to ground of the system. V SS NC – No Con
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 access (read, write, or deselect) is latched into the Address , CE , and CE ) and WE inputs clock rise, the Chip Enables (CE 1 2 3 Register (provided the appropriate control signals are asserted). are ignored and the burst counter is incremented. The correct BW (BW for CY7C1470BV33, BW for CY7C1472V33, a,b,c,d a,b and DQP On the next clock rise the data presented to DQ and BW for CY7C1474BV33) inputs must be driven a,b,c,d,e,f,g,h (DQ /DQP for CY7C1470BV
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Table 4. Truth Table [1, 2, 3, 4, 5, 6, 7] The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Operation Address Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Deselect Cycle None H L L X X X L L-H Tri-State Continue None X L H X X X L L-H Tri-State Deselect Cycle Read Cycle External L L L H X L L L-H Data Out (Q) (Begin Burst) Read Cycle Next X L H X X L L L-H Data Out (Q) (Continue Burst) NOP/Dummy Read External L L L H X H L L-H Tri-Stat
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Table 5. Partial Write Cycle Description [1, 2, 3, 8] The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Function (CY7C1470BV33) WE BW BW BW BW d c b a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ and DQP)LHHHL a a Write Byte b – (DQ and DQP)LHHLH b b Write Bytes b, a L H H L L Write Byte c – (DQ and DQP)LHLHH c c Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Test Mode Select (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 and is sampled on the rising edge of TCK. It is allowable to leave incorporates a serial boundary scan test access port (TAP). This this ball unconnected if the TAP is not used. The ball is pulled up port operates in accordance with IEEE Standard 1149.1-1990 internally, resulting in a l
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Instruction Register Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and Three-bit instructions can be serially loaded into the instruction TDO. During this state, instructions are shifted through the register. This register is loaded when it is placed between the TDI instruction register through the TDI and TDO balls. To execute and TDO balls as shown in the “TAP Controller Bloc
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 possible to capture all other signals and simply ignore the value BYPASS of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary placed between the TDI and TDO balls. The advantage of the scan regist
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 TAP AC Switching Characteristics [9, 10] Over the Operating Range Parameter Description Min Max Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hol
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels.................................................V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times....................................................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels........................................... 1.5V I
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Table 6. Identification Register Definitions CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 Instruction Field Description (2M x 36) (4M x 18) (1M x 72) Revision Number (31:29) 000 000 000 Describes the version number [12] Device Depth (28:24) 01011 01011 01011 Reserved for internal use Architecture/Memory 001000 001000 001000 Defines memory type and archi- Type(23:18) tecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density Cypress JEDEC ID
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Table 9. Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3E1 23 R4 43 J10 63 A6 4D2 24 P6 44 H11 64 B5 5E2 25 R6 45 G11 65 A5 6F1 26 R8 46 F11 66 A4 7G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1A1 29 T1 57 U10 85 B11 2A2 30 T2 58 T11 86 B10 3B1 31 U1 59 T10 87 A11 4B2 32 U2 60 R11 88 A10 5C1 33 V1 61 R10 89 A7 6C2 34 V2 62 P11 90 A5 7D1 35 W1 63 P10 91 A9 8D2 36 W2 64 N11 92 U8 9E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J1
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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 + 0.5V DC Input Voltage ................................... –0.5V to V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage.......................................... > 2001V device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch Up Current
