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CY8C24123A
CY8C24223A, CY8C24423A
®
PSoC Programmable System-on-Chip™
■ New CY8C24x23A PSoC Device
Features
❐ Derived From the CY8C24x23 Device
■ Powerful Harvard Architecture Processor
❐ Low Power and Low Voltage (2.4V)
❐ M8C Processor Speeds to 24 MHz
■ Additional System Resources
❐ 8x8 Multiply, 32-Bit Accumulate
2
❐ I C™ Slave, Master, and MultiMaster to 400 kHz
❐ Low Power at High Speed
❐ Watchdog and Sleep Timers
❐ 2.4 to 5.25V Operating Voltage
❐ User-Configurable Low Voltage Detection
❐
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Row Output Configuration Digital Clocks From Core CY8C24123A CY8C24223A, CY8C24423A ® Digital System PSoC Functional Overview The Digital System consists of 4 digital PSoC blocks. Each block The PSoC family consists of many Mixed-Signal Array with is an 8-bit resource that may be used alone or combined with On-Chip Controller devices. These devices are designed to other blocks to form 8, 16, 24, and 32-bit peripherals, which are replace multiple traditional MCU-based system components with cal
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CY8C24123A CY8C24223A, CY8C24423A Figure 2. Analog System Block Diagram Analog System The Analog System consists of six configurable blocks, each P0[7] P0[6] consisting of an opamp circuit that allows the creation of complex P0[5] P0[4] analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. P0[3] P0[2] Some of the more common PSoC analog functions (most P0[1] P0[0] available as user modules) are: ■ Analog-to-digital converte
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CY8C24123A CY8C24223A, CY8C24423A Additional System Resources Getting Started System Resources, some of which are listed in the previous The quickest path to understanding the PSoC silicon is by sections, provide additional capability useful to complete reading this data sheet and using the PSoC Designer Integrated systems. Additional resources include a multiplier, decimator, Development Environment (IDE). This data sheet is an overview switch mode pump, low voltage detection, and power on rese
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Results CY8C24123A CY8C24223A, CY8C24423A PSoC Designer Software Subsystems Development Tools ® Device Editor PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable The Device Editor subsystem allows the user to select different System-on-Chip (PSoC) devices. The PSoC Designer IDE and onboard analog and digital components called user modules application runs on Windows NT 4.0, Windows 2000, Windows using the PSoC blocks. Examples of user modules are A
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CY8C24123A CY8C24223A, CY8C24423A Debugger establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user The PSoC Designer Debugger subsystem provides hardware module application programming interface (API) provides in-circuit emulation, allowing the designer to test the program in high-level functions to control and respond to hardware events a physical system while providing an internal view of the PSoC at run-time. The API also prov
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CY8C24123A CY8C24223A, CY8C24423A The next step is to write your main program, and any sub-routine Table 2. Acronyms Used (continued) using PSoC Designer’s Application Editor subsystem. The Acronym Description Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code LSb least-significant bit files) from a hierarchal view. The source code editor provides LVD low voltage detect syntax coloring and advanced edit features for
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CY8C24123A CY8C24223A, CY8C24423A Pinouts This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 8-Pin Part Pinoutt Table 3. Pin Definitions - 8-Pin PDIP and SOIC Type Figure 5. CY8C24123A 8-Pin PSoC Device Pin Pin Description No. Name Digital Analog 1 IO IO P0[5] Analog Column Mux Input and A, IO, P0[5] 1 8 Vdd PDIP
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CY8C24123A CY8C24223A, CY8C24423A 20-Pin Part Pinout Table 4. Pin Definitions - 20-Pin PDIP, SSOP, and SOIC Type Figure 6. CY8C24223A 20-Pin PSoC Device Pin Pin Description No. Name Digital Analog A, I, P0[7] Vdd 1 20 1 IO I P0[7] Analog Column Mux Input A, IO, P0[5] 2 19 P0[6], A, I 2 IO IO P0[5] Analog Column Mux Input and Column A, IO, P0[3] 3 18 P0[4], A, I Output A, I, P0[1] P0[2], A, I 4 17 PDIP SMP 5 16 P0[0], A, I 3 IO IO P0[3] Analog Column Mux Input and Column SSOP I2 C S C L
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CY8C24123A CY8C24223A, CY8C24423A 28-Pin Part Pinout Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC Type Figure 7. CY8C24423A 28-Pin PSoC Device Pin Pin Description No. Name Digital Analog A, I, P0[7] 1 Vdd 1 IO I P0[7] Analog Column Mux Input 28 A, IO, P0[5] P0[6], A, I 2 27 2 IO IO P0[5] Analog Column Mux Input and column A, IO, P0[3] 3 26 P0[4], A, I output A, I, P0[1] P0[2], A, I 4 25 3 IO IO P0[3] Analog Column Mux Input and Column P2[7] P0[0], A, I 5 24 Output P2[5] 6 23 P
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CY8C24123A CY8C24223A, CY8C24423A 32-Pin Part Pinout Table 6. Pin Definitions - 32-Pin QFN** Type Figure 8. CY8C24423A 32-Pin PSoC Device Pin Pin Description No. Name Digital Analog 1 IO P2[7] 2 IO P2[5] 3 IO I P2[3] Direct Switched Capacitor Block Input P2[7] 1 24 P0[2], A, I 4 IO I P2[1] Direct Switched Capacitor Block Input P2[5] P0[0], A, I 2 23 A, I, P2[3] 3 22 P2[6], External VRef 5 Power Vss Ground Connection A, I, P2[1] 4 21 P2[4], External AGND QFN Vss 5 20 P2[2], A, I 6 Power SMP S
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CY8C24123A CY8C24223A, CY8C24423A 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. Pin Definitions - 56-Pin SSOP Type Pin Pin Description No. Name Digital Analog 1 NC No Connection Figure 10. CY8C24000A 56-Pin PSoC Device 2 IO I P0[7] Analog Column Mux Input NC 1 56 Vdd 3 IO I P0[5] Analog Column Mux Input and AI, P0[7]255 P0[6], AI Column Output
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CY8C24123A CY8C24223A, CY8C24423A Table 7. Pin Definitions - 56-Pin SSOP (continued) Type Pin Pin Description No. Name Digital Analog 34 IO P1[6] 35 IO P5[0] 36 IO P5[2] 37 IO P3[0] 38 IO P3[2] 39 IO P3[4] 40 IO P3[6] 41 Input XRES Active high external reset with internal pull down. 42 OCD HCLK OCD high-speed clock output. 43 OCD CCLK OCD CPU clock output. 44 IO P4[0] 45 IO P4[2] 46 IO P4[4] 47 IO P4[6] 48 IO I P2[0] Direct switched capacitor block input. 49 IO I P2[2] Direct switched capac
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CY8C24123A CY8C24223A, CY8C24423A Register Mapping Tables Register Reference The PSoC device has a total register address space of 512 This section lists the registers of the CY8C24x23A PSoC device. bytes. The register space is referred to as IO space and is For detailed register information, refer the PSoC Programmable divided into two banks. The XOI bit in the Flag register (CPU_F) Sytem-on-Chip Reference Manual. determines which bank the user is currently in. When the XOI bit is set the user
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CY8C24123A CY8C24223A, CY8C24423A Table 9. Register Map Bank 0 Table: User Space Addr Addr Addr Addr Name Access Name Access Name Access Name Access (0,Hex) (0,Hex) (0,Hex) (0,Hex) PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9
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CY8C24123A CY8C24223A, CY8C24423A Table 9. Register Map Bank 0 Table: User Space (continued) Addr Addr Addr Addr Name Access Name Access Name Access Name Access (0,Hex) (0,Hex) (0,Hex) (0,Hex) 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and must not be accessed. # Access is bit specific. Table 10. Register Map Bank 1 Table: Configuration Space Addr Addr Addr Addr Name Access Name Access Name Access Name Access (1,Hex) (1,Hex) (1,Hex) (1,Hex) PRT0DM0 00 RW 40 ASC
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CY8C24123A CY8C24223A, CY8C24423A Table 10. Register Map Bank 1 Table: Configuration Space (continued) Addr Addr Addr Addr Name Access Name Access Name Access Name Access (1,Hex) (1,Hex) (1,Hex) (1,Hex) 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 38-12028 Rev. *I Page 17 of 56 [+] Feedback
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Vdd Vo ltag e Vdd Vo ltag e Valid Operating Region CY8C24123A CY8C24223A, CY8C24423A Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications, check if you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Specifications are valid for -40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. A J Refer to Table 31 on page 32 for the electrical specifications on the i
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CY8C24123A CY8C24223A, CY8C24423A Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes T Storage Temperature -55 25 +100 °C Higher storage temperatures STG reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrades reliability. T Ambient Temperature with Power App
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CY8C24123A CY8C24223A, CY8C24423A DC Electrical Characteristics DC Chip-Level Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to A A A 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. Table 14. DC Chip-Level Specifications Symbol Description Min Typ Max Units Not
