Краткое содержание страницы № 1
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
1.8V 4k/8k/16k x 16 and 8k/16k x 8
ConsuMoBL Dual-Port Static RAM
• Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package
Features
• Full asynchronous operation
• True dual-ported memory cells which allow simulta-
• Pin select for Master or Slave
neous access of the same memory location
• Expandable data bus to 32 bits with Master/Slave chip
• 4/8/16k × 16 and 8/16k × 8 organization
select when using more than one device
• High-speed
Краткое содержание страницы № 2
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 I/O[15:0] R I/O[15:0] L UB R UB L LB LB L R IO IO Control Control 16K X 16 Dual Ported Array Address Decode Address Decode A[13:0] A [13:0] L R CE CE L R Interrupt OE OE L Arbitration R R/W R/W R Semaphore L SEM SEM R L BUSY BUSY R L M/S INT Mailboxes INT L R Input Read Register and CE CE L R Output Drive OE OE L R Register R/W R/W L R IRR ,IRR 0 1 ODR - ODR 0 4 SFEN [1, 2] Figure 1. Top Level Block Diagram Notes: 1. A –A fo
Краткое содержание страницы № 3
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 [3, 4, 5, 6, 7] Pin Configurations 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A 1 75 A 4L 4R A 2 74 A 5L 5R A 3 73 A 6L 6R 72 A A 4 7L 7R A 5 71 A 8L 8R CE 6 70 CE L R SEM 7 69 SEM L R INT 8 68 INT L R BUSY 9 67 BUSY L R CYDC064B16 A 10 66 A 9L 9R A 11 65 A 10L 10R CYDC128B16 V 12 64 V SS SS CYDC256B16 V 13 63 V CC CC A 14 62 A 11L 11R [3] [3] A 15 61 A 12L 12R [5] [6] IRR0 16 60 I
Краткое содержание страницы № 4
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 [7, 8, 9, 10] Pin Configurations (continued) 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A 1 75 A 4L 4R A 2 74 A 5L 5R A 3 73 A 6L 6R A 4 72 A 7R 7L A 5 71 A 8L 8R CE 6 70 CE L R SEM 7 69 SEM L R INT 8 68 INT L R BUSY 9 67 BUSY L R A 10 66 A 9L 9R A 11 65 A 10L 10R CYDC064B08 V 12 64 V SS SS V 13 63 V CC CC CYDC128B08 A 14 62 A 11L 11R A 15 61 A 12L 12R [9] [10] IRR0 16 60 IRR1 [11]
Краткое содержание страницы № 5
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Pin Definitions Left Port Right Port Description CE CE Chip Enable L R R/W R/W Read/Write Enable L R OE OE Output Enable L R A –A A –A Address (A –A for 4k devices; A –A for 8k devices; A –A for 16k devices). 0L 13L 0R 13R 0 11 0 12 0 13 I/O –I/O I/O –I/O Data Bus Input/Output for x16 devices; I/O –I/O for x8 devices. 0L 15L 0R 15R 0 7 SEM SEM Semaphore Enable L R UB UB Upper Byte Select (I/O –I/O for x16 devices; Not applicable for x8
Краткое содержание страницы № 6
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 then the SEM pin must be asserted instead of the CE pin, and The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL, OE must also be asserted. depending on the core voltage supply (V ). Refer to Table 3 CC for Input Read Register operation. Interrupts IRR is not available in the CYDC256B16 and CYDC128B08, The upper two memory locations may be used for message as the IRR pins are used as extra address pins A and A . 13L 13R passing. The highes
Краткое содержание страницы № 7
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 When reading a semaphore, all sixteen/eight data lines output CYDC128B08 consist of an array of 8k and 16k words of 8 the semaphore value. The read value is latched in an output each of dual-port RAM cells, I/O and address lines, and control register to prevent the semaphore from changing state during signals (CE, OE, R/W).These control pins permit independent a write from the other port. If both ports attempt to access the access for re
Краткое содержание страницы № 8
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 [16, 19] Table 3. Input Read Register Operation SFEN CE R/W OE UB LB ADDR I/O –I/O I/O –I/O Mode 0 1 2 15 [17] [17] HLHL L L x0000-MaxVALID VALID Standard Memory Access [18] L L H L X L x0000 VALID X IRR Read [20] Table 4. Output Drive Register SFEN CE R/W OE UB LB ADDR I/O –I/O I/O –I/O Mode 0 4 5 15 [21] [17] [17] [17] [17] HLH X L L x0000-Max VALID VALID Standard Memory Access [18] [20, 22] LL L X X L x0001VALID X ODR Write [18] [20
Краткое содержание страницы № 9
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 [23] Output Current into Outputs (LOW)............................. 90 mA Maximum Ratings Static Discharge Voltage.......................................... > 2000V (Above which the useful life may be impaired. For user guide- Latch-up Current.................................................... > 200 mA lines, not tested.) Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Range
Краткое содержание страницы № 10
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Electrical Characteristics for V = 1.8V (continued) Over the Operating Range CC CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 -40 -55 P1 I/O P2 I/O Parameter Description Voltage Voltage Min. Typ. Max. Min. Typ. Max. Unit I Input Leakage Current 1.8V 1.8V –1 1 –1 1 µA IX 2.5V 2.5V –1 1 –1 1 µA 3.0V 3.0V –1 1 –1 1 µA I Operating Current (V = Max., Ind. 1.8V 1.8V 2
Краткое содержание страницы № 11
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Electrical Characteristics for V = 2.5V Over the Operating Range CC CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 -40 -55 P1 I/O P2 I/O Parameter Description Voltage Voltage Min. Typ. Max. Min. Typ. Max. Unit V Output HIGH Voltage (I = –2 mA) 2.5V (any port) 2.0 2.0 V OH OH Output HIGH Voltage (I = –2 mA) 3.0V (any port) 2.1 2.1 V OH V Output LOW Voltage (I = 2
Краткое содержание страницы № 12
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Electrical Characteristics for 3.0V Over the Operating Range CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 -40 -55 P1 I/O P2 I/O Parameter Description Voltage Voltage Min. Typ. Max. Min. Typ. Max. Unit V Output HIGH Voltage (I = –2 mA) 3.0V (any port) 2.1 2.1 V OH OH V Output LOW Voltage (I = 2 mA) 3.0V (any port) 0.4 0.4 V OL OL V ODR ODR Output LOW Voltage (
Краткое содержание страницы № 13
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 7 AC Test Loads and Waveforms 3.0V/2.5V/1.8V 3.0V/2.5V/1.8V R1 R = 6 kΩ TH OUTPUT OUTPUT R1 C = 30 pF OUTPUT C = 30 pF R2 C = 5 pF R2 V = 0.8V TH (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (b) Thévenin Equivalent (Load 1) (Used for t , t , t , and t ALL INPUT PULSES LZ HZ HZWE LZWE 3.0V/2.5V 1.8V including scope and jig) 1.8V R1 1022Ω 13500Ω 90% 90% 10% 10% R2 792Ω 10800Ω GND ≤ 3 ns ≤ 3 ns [27] Switching Characteristics for
Краткое содержание страницы № 14
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 [27] Switching Characteristics for V = 1.8V Over the Operating Range (continued) CC CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 -40 -55 Parameter Description Min. Max. Min. Max. Unit t Address Hold From Write End 0 0 ns HA [28] t Address Set-up to Write Start 0 0 ns SA t Write Pulse Width 25 40 ns PWE t Data Set-up to Write End 20 30 ns SD t Data Hold From Writ
Краткое содержание страницы № 15
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for V = 2.5V Over the Operating Range CC CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 -40 -55 Parameter Description Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 40 55 ns RC t Address to Data Valid 40 55 ns AA t Output Hold From Address Change 5 5 ns OHA [28] t CE LOW to Data Valid 40 55 ns ACE t OE LOW to Data Valid 25 30 ns DO
Краткое содержание страницы № 16
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for V = 2.5V Over the Operating Range (continued) CC CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 -40 -55 Parameter Description Min. Max. Min. Max. Unit [33] Interrupt Timing t INT Set Time 35 45 ns INS t INT Reset Time 35 45 ns INR Semaphore Timing t SEM Flag Update Pulse (OE or SEM)10 15 ns SOP t SEM Flag Write to Read Time 10 10 ns S
Краткое содержание страницы № 17
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for V = 3.0V Over the Operating Range (continued) CC CYDC256B16, CYDC256B16, CYDC128B16, CYDC128B16, CYDC064B16, CYDC064B16, CYDC128B08, CYDC128B08, CYDC064B08 CYDC064B08 Unit -40 -55 Parameter Description Min. Max. Min. Max. [30, 31] t R/W LOW to High Z 15 25 ns HZWE [30, 31] t R/W HIGH to Low Z 0 0 ns LZWE [32] t Write Pulse to Data Delay 55 80 ns WDD [32] t Write Data Valid to Read Data Valid 55 80 ns DDD
Краткое содержание страницы № 18
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms [36, 37, 38] Read Cycle No.1 (Either Port Address Access) t RC ADDRESS t AA t t OHA OHA DATA OUT PREVIOUS DATA VALID DATA VALID [36, 39, 40] Read Cycle No.2 (Either Port CE/OE Access) t ACE CE and LB or UB t HZCE t DOE OE t HZOE t LZOE DATA VALID DATA OUT t LZCE t PU t PD I CC CURRENT I SB [36, 38, 41, 42] Read Cycle No. 3 (Either Port) t RC ADDRESS t t AA OHA UB or LB t HZCE t LZCE t ABE CE t HZCE t ACE t LZCE DATA O
Краткое содержание страницы № 19
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) [41, 42, 43, 44, 45, 46] Write Cycle No.1: R/W Controlled Timing t WC ADDRESS [47] t HZOE OE t AW [45, 46] CE [44] t t t SA PWE HA R/W [47] t HZWE t LZWE NOTE 48 NOTE 48 DATA OUT t t SD HD DATA IN [41, 42, 43, 48] Write Cycle No. 2: CE Controlled Timing t WC ADDRESS t AW [45, 46] CE t t t SA SCE HA R/W t t SD HD DATA IN Notes: 43. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at t
Краткое содержание страницы № 20
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) [49, 50] Semaphore Read After Write Timing, Either Side t t SAA OHA A –A VALID ADRESS VALID ADRESS 0 2 t AW t ACE t HA SEM t t SCE SOP t SD I/O 0 DATA VALID DATA VALID IN OUT t HD t t SA PWE R/W t t SWRD DOE t OE SOP WRITE CYCLE READ CYCLE [51, 52] Timing Diagram of Semaphore Contention A –A 0L 2L MATCH R/W L SEM L t SPS A –A 0R 2R MATCH R/W R SEM R Notes: 49. If the CE or SEM LOW transition occurs simu
