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CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
[1]
Features Functional Description
• Supports 133 MHz bus operations The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a
3.3V, 512K x 36 and 1M x 18 synchronous flow through
• 512K × 36 and 1M × 18 common IO
SRAMs, designed to interface with high-speed
• 3.3V core power supply (V )
DD microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
• 2.5V or 3
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [3] Logic Block Diagram – CY7C1381D/CY7C1381F (512K x 36) ADDRESS A0, A1, A REGISTER A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTE BYTE WRITE REGISTER WRITE REGISTER WRITE REGISTER DQ C , DQP C DQ C , DQP C BW C WRITE REGISTER OUTPUT WRITE REGISTER DQs MEMORY SENSE BUFFERS ARRAY DQP A DQ B, DQP B AMPS DQ B, DQP B DQP B BW B DQP C WRITE REGISTER DQP D WRITE REGISTER DQ A, DQP DQ A, DQP A BYTE BW A
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Pin Configurations 100-pin TQFP Pinout (3 Chip Enable) DQP C DQP 1 80 NC B 1 80 A DQ DQ C 2 79 NC B 2 79 NC DQ C 3 78 DQ B NC 3 78 NC V DDQ 4 77 V DDQ V DDQ V 4 77 DDQ V SSQ 5 76 V SSQ V SSQ V 5 76 SSQ DQ C 6 75 DQ B NC NC 6 75 DQ C 7 74 DQ B NC DQP 7 74 A DQ C DQ 8 73 DQ B B 8 73 DQ A DQ C DQ 9 72 DQ B B 9 72 DQ A V SSQ V 10 71 V SSQ SSQ 10 71 V SSQ V V DDQ 11 70 V DDQ DDQ 11 70 V DDQ DQ DQ C 12 69 B DQ B 12 69 DQ A DQ C 13 68 DQ B DQ B DQ 13 68 A V /DN
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Pin Configurations (continued) 119-Ball BGA Pinout CY7C1381F (512K x 36) 1 23 4 5 6 7 A V AA A A V DDQ ADSP DDQ B NC/288M AA A A NC/576M ADSC C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V V DQ DQ CE C C SS SS B B 1 F V DQ V V DQ V DDQ C SS OE SS B DDQ G DQ DQ ADV DQ DQ BW BW C C B B C B H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D A A D
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381D (512K x 36) 1 23 4 5 6 7 89 10 11 NC/288M CE BW BW CE BWE ADSC ADV A NC A A 1 C B 3 NC/144M A CE BW BW CLK GW OE ADSP A NC/576M B 2 D A C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Pin Definitions Name IO Description A , Input- Address inputs used to select one of the address locations. Sampled at the rising edge A , A 0 1 [2] Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. 1 2 3 A feed the 2-bit counter. [1:0] BW , BW Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the A B BW , BW Synchronous SRAM. Sampled on the rising edge of CLK. C D GW
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Pin Definitions (continued) Name IO Description MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V DD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. V Power Supply Power supply inputs to the core of the device. DD V IO Power Supply Power supply for the IO circuitry. DDQ V Ground Ground for the co
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F deasserted and the IOs must be tri-stated prior to the presen- Sleep Mode tation of data to DQs. As a safety precaution, the data lines are The ZZ input pin is an asynchronous input. Asserting ZZ tri-stated once a write cycle is detected, regardless of the state places the SRAM in a power conservation sleep mode. Two of OE. clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Single Write
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [4, 5, 6, 7, 8] Truth Table ADDRESS Cycle Description Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselected Cycle, Power None H X X L X L X X X L-H Tri-State Down Deselected Cycle, Power None L L X L L X X X X L-H Tri-State Down Deselected Cycle, Power None L X H L L X X X X L-H Tri-State Down Deselected Cycle, Power None L L X L H L X X X L-H Tri-State Down Deselected Cycle, Power None X X X L H L X X X L-H Tri-State Down Sleep Mode, Power D
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [4, 9] Truth Table for Read/Write Function (CY7C1381D/CY7C1381F) GW BWE BW BW BW BW D C B A Read H H XXX X Read H L HHH H Write Byte A (DQ , DQP) H L HHH L A A Write Byte B(DQ , DQP)HLHHLH B B Write Bytes A, B (DQ , DQ , DQP , DQP)H L H H L L A B A B Write Byte C (DQ , DQP) H LH LH H C C Write Bytes C, A (DQ , DQ DQP , DQP) H LH LHL C A, C A Write Bytes C, B (DQ , DQ DQP , DQP)H L H L L H C B, C B Write Bytes C, B, A (DQ , DQ , DQ DQP , HLH L L L C B A,
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F registers. The register between TDI and TDO is chosen by the IEEE 1149.1 Serial Boundary Scan (JTAG) instruction that is loaded into the TAP instruction register. TDI The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is internally pulled up and can be unconnected if the TAP is incorporates a serial boundary scan test access port unused in an application. TDI is connected to the most (TAP).This part is fully compliant with 1149.1. The TAP significant bit (MSB)
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Bypass Register The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test To save time when serially shifting data through registers, it is logic reset state. sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the SAMPLE Z TDI and TDO balls. This allows data to be shifted through the The SAMPLE Z instruction causes the boun
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F (Q-bus) pins, when the EXTEST is entered as the current directly control the output Q-bus pins. Note that this bit is instruction. When HIGH, it will enable the output buffers to preset HIGH to enable the output when the device is powered drive the output bus. When LOW, this bit will place the output up, and also when the TAP controller is in the Test-Logic-Reset bus into a High-Z condition. state. This bit can be set by entering the SAMPLE/PRELOAD or R
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels .................................................V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Identification Register Definitions CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F Instruction Field (512K × 36) (1M × 18) Description Revision Number (31:29) 000 000 Describes the version number. [13] Device Depth (28:24) 01011 01011 Reserved for internal use. Device Width (23:18) 119-BGA 101001 101001 Defines the memory type and architecture. Device Width (23:18) 165-FBGA 000001 000001 Defines the memory type and architecture. Cypress Device ID (17:12) 1001
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [14, 15] 119-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 23 F6 45 G4 67 L1 H4 2 T4 24 E746 A468 M2 3T5 25 D7 47 G3 69 N1 4 T6 26 H748 C370 P1 5R5 27 G6 49 B2 71 K1 6 L5 28 E650 B372 L2 7R6 29 D6 51 A3 73 N2 8 U6 30 C752 C274 P2 9 R7 31 B753 A275 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [14, 16] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N7 32 C11 62 D2 3 N10 33 A11 63 E2 4P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage........................................... > 2001V the device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Curr
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [19] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit C Input Capacitance T = 25°C, f = 1 MHz, 58 9 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 8 9 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 8 9 pF IO [19] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 28.66 23.8 20.7
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Switching Characteristics [20, 21] Over the Operating Range 133 MHz 100 MHz Parameter Description Min Max Min Max Unit [22] t V (Typical) to the first Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 2.1 2.5 ns CH t Clock LOW 2.1 2.5 ns CL Output Times t Data Output Valid After CLK Rise 6.5 8.5 ns CDV t Data Output Hold After CLK Rise 2.0 2.0 ns DOH [23, 24, 25] t Clock to Low-Z 2.0 2.0 ns CLZ [23, 24, 25] t Clock to High-Z 0 4.
