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CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Features Functional Description
■ No Bus Latency™ (NoBL™) architecture eliminates dead The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
cycles between write and read cycles are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
■ Supports up to 133 MHz bus operations with zero wait states
back-to-back read or write ope
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Logic Block Diagram – CY7C1471BV25 (2M x 36) ADDRESS A0, A1, A A1 REGISTER A1' D1 Q1 A0 A0' D0 Q0 MODE BURST CE ADV/LD LOGIC CLK C CEN C WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F T BW B AND DATA COHERENCY DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1473BV25 (4
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Logic Block Diagram – CY7C1475BV25 (1M x 72) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U ADV/LD A T N T T S A BW a R MEMORY E B WRITE DQ s BW b E U ARRAY S G DRIVERS A F BW c T DQ Pa WRITE REGISTRY I M F E AND DATA COHERENCY S DQ Pb BW d P E E T CONTROL LOGIC S R R DQ Pc BW e E I S R DQ Pd BW f N S G BW g DQ Pe E E BW h DQ Pf DQ Pg DQ
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations Figure 1. 100- Pin TQFP Pinout DQP 80 1 C DQP B DQ 79 C 2 DQ B DQ 78 3 C DQ B V 77 4 V DDQ DDQ V 76 5 SS V SS DQ 75 C 6 DQ B BYTE C BYTE B DQ 74 7 C DQ B DQ 73 8 DQ C B DQ 72 9 C DQ B V 71 SS 10 V SS V 70 11 DDQ V DDQ DQ 69 C 12 DQ B DQ 68 13 C DQ B CY7C1471BV25 NC 67 14 V SS V 66 15 NC DD NC 65 16 V DD V 64 ZZ 17 SS DQ 63 D 18 DQ A DQ 62 19 DQ D A V 61 20 DDQ V DDQ V 60 21 V SS SS DQ 59 22 D DQ A DQ 58 23 DQ BYTE D D A BYTE A DQ 57
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations (continued) Figure 2. 100-Pin TQFP Pinout NC 80 1 A NC 79 2 NC NC 78 3 NC V 77 4 V DDQ DDQ V 76 5 SS V SS NC 75 6 NC NC 74 7 DQP A DQ 73 B 8 DQ A DQ 72 9 B DQ A V 71 SS 10 V SS V 70 11 V DDQ DDQ DQ 69 B 12 DQ A DQ 68 13 DQ B A NC 67 14 V SS BYTE A V 66 15 NC DD NC 65 16 CY7C1473BV25 BYTE B V DD V 64 ZZ 17 SS DQ 63 18 B DQ A DQ 62 19 DQ B A V 61 20 DDQ V DDQ V 60 21 V SS SS DQ 59 22 B DQ A DQ 58 23 DQ B A DQP 57 24 NC B NC 56 25 NC V
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV25 (2M x 36) 1 234 5 6 7 89 10 11 A NC/576M CE BW BW CE CEN ADV/LD A NC A A 1 C B 3 NC/1G A CE2 CLK A A NC B BW BW WE OE D A DQP NC V V V V V V V NC DQP C C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DD SS SS DD B B DDQ SS DDQ DQ DQ V V V V V V V DQ DQ E C C DD SS SS DD B B DDQ SS DDQ DQ V V V DQ F DQ V V V V DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1475BV25 (1M × 72) 12 3 4 5 6 7 8 9 10 11 DQb A DQg DQgAA CE ADV/LDA CEA DQb 2 3 B DQg DQg BWS BWS NC WE A BWS BWS DQb DQb c g b f DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb C h d 1 e a D DQg DQg V NC NC/1G OE NC NC V DQb DQb SS SS E DQPg DQPc V V V V V V V DDQ DDQ DD DDQ DDQ DQPf DQPb DD DD DQc F DQc V V V V DQf V NC V SS SS SS SS DQf SS SS G DQc V V DQc V V V DDQ NC DD V DDQ
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 1. Pin Definitions Name IO Description A , A , A Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge 0 1 Synchronous of the CLK. A are fed to the two-bit burst counter. [1:0] , BW , Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled BW A B BW , BW , Synchronous on the rising edge of CLK. C D BW , BW , E F BW , BW G H WE Input- Write Enable Input, Active LOW. S
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 1. Pin Definitions (continued) Name IO Description TDI JTAG serial input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not used, leave this pin floating or connected to V through a pull up resistor. This pin is not DD available on TQFP packages. TMS JTAG serial input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not used, this
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 included to greatly simplify read/modify/write sequences, which Table 2. Interleaved Burst Address Table can be reduced to simple byte write operations. (MODE = Floating or V ) DD Because the CY7C1471BV25, CY7C1473BV25, and First Second Third Fourth CY7C1475BV25 are common IO devices, data must not be Address Address Address Address driven into the device while the outputs are active. The OE can A1: A0 A1: A0 A1: A0 A1: A0 be deasserted HIGH before prese
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 4. Truth Table [1, 2, 3, 4, 5, 6, 7] The truth table for CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 follows. Address Operation CE CE ZZ ADV/LD WE BW OE CEN CLK DQ CE 1 2 X 3 Used Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Continue Deselect Cycle None X X X L H X X X L L->H Tri-State Read Cycle External L H L L L H X L L L->H Data O
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 5. Truth Table for Read/Write [1, 2, 8] The read-write truth table for CY7C1471BV25 follows. Function WE BW BW BW BW A B C D Read H X XXX Write No bytes written L H H H H Write Byte A – (DQ and DQP) L L HHH A A Write Byte B – (DQ and DQP)LHLHH B B Write Byte C – (DQ and DQP)LHHLH C C Write Byte D – (DQ and DQP)LHHHL D D Write All Bytes L LLLL Table 6. Truth Table for Read/Write [1, 2, 8] The read-write truth table for CY7C1473BV25 follows. Functio
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Test Access Port (TAP) IEEE 1149.1 Serial Boundary Scan (JTAG) Test Clock (TCK) The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 incorporate a serial boundary scan Test Access Port (TAP). This The test clock is used only with the TAP controller. All inputs are port operates in accordance with IEEE Standard 1149.1-1990 captured on the rising edge of TCK. All outputs are driven from but does not have the set of functions required for full 1149.1 the falling
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 Registers are connected between the TDI and TDO balls and instructions are not fully implemented. enable the scanning of data into and out of the SRAM test You cannot use the TAP controller to load address data or control circuitry. Only one register is selectable at a time through the signals into the SRAM and you cannot
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 no guarantee as to the value that is captured. Repeatable results Note that since the PRELOAD part of the command is not imple- may not be possible. mented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the To guarantee that the boundary scan register captures the Pause-DR command. correct signal value, make certain that the SRAM signal is stabi- lized long enough to meet the TAP controller’s ca
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 TAP AC Switching Characteristics [9, 10] Over the Operating Range Parameter Description Min Max Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH Time 20 ns TH t TCK Clock LOW Time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hol
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 8. Identification Register Definitions CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Instruction Field Description (2MX36) (4MX18) (1MX72) Revision Number (31:29) 000 000 000 Describes the version number Device Depth (28:24) 01011 01011 01011 Reserved for internal use Architecture/Memory Type(23:18) 001001 001001 001001 Defines memory type and architecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density Cypress JEDEC ID Code (11:1)
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 11. Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C121 R341 J11 61 B7 2D1 22 P2 42 K10 62 B6 3E1 23 R4 43 J10 63 A6 4D2 24 P6 44 H11 64 B5 5E2 25 R6 45 G11 65 A5 6F1 26 R8 46 F11 66 A4 7G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 3
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Table 13. Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2A2 30 T2 58 T11 86 B10 3B1 31 U1 59 T10 87 A11 4B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6C2 34 V2 62 P11 90 A5 7D1 35 W1 63 P10 91 A9 8D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15
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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage........................................... >2001V device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch Up Current .
