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CY7C1361C
CY7C1363C
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
[1]
Features Functional Description
• Supports 100, 133-MHz bus operations The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through SRAMs, respectively designed to
• Supports 100-MHz bus operations (Automotive)
interface with high-speed microprocessors with minimum glue
• 256K × 36/512K × 18 common I/O
logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter capture
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CY7C1361C CY7C1363C Logic Block Diagram – CY7C1361C (256K x 36) ADDRESS A0, A1, A REGISTER A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD, DQPD DQD, DQPD BYTE BWD BYTE BYTE WRITE REGISTER WRITE REGISTER WRITE REGISTER DQC, DQPC DQC, DQPC BYTE BWC BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQs MEMORY SENSE BUFFERS DQPA ARRAY DQB, DQPB AMPS DQB, DQPB DQPB BYTE BWB BYTE DQPC WRITE REGISTER DQPD WRITE REGISTER DQA, DQPA DQA, DQPA BYTE BWA BYTE WRITE REGISTER BWE WRITE REGIS
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CY7C1361C CY7C1363C Pin Configurations 100-Pin TQFP Pinout (3 Chip Enables) (A version) DQP C DQP 1 80 NC B 1 80 A DQ C DQ 2 79 NC B 2 79 NC DQ C DQ 3 78 NC B NC 3 78 V DDQ V 4 77 V DDQ DDQ 4 77 V DDQ V SSQ 5 76 V V SSQ V SSQ 5 76 SSQ DQ C 6 75 DQ B NC NC 6 75 DQ C 7 74 DQ B NC DQP 7 74 A DQ C 8 73 DQ B DQ B DQ 8 73 A DQ C 9 72 DQ B DQ B DQ 9 72 A V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQ C 12 69 DQ B DQ B DQ 12 69 A DQ C 13 68 DQ B DQ B DQ 13 68 A V /DNU SS 1
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CY7C1361C CY7C1363C Pin Configurations (continued) 100-Pin TQFP Pinout (2 Chip Enables) (AJ Version) DQP C 1 80 DQP B NC A 1 80 DQ C 2 79 DQ B NC NC 2 79 DQ C 3 78 DQ B NC NC 3 78 V DDQ 4 77 V V DDQ V DDQ 4 77 DDQ V SSQ V 5 76 V SSQ SSQ 5 76 V SSQ DQ C DQ 6 75 NC B 6 75 NC DQ C DQ 7 74 NC B 7 74 DQP A DQ C DQ 8 73 DQ B B 8 73 DQ A DQ DQ C 9 72 DQ B B 9 72 DQ A V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQ C 12 69 DQ B DQ B DQ 12 69 A DQ C 13 68 DQ B DQ B DQ 13 68
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CY7C1361C CY7C1363C Pin Configurations (continued) 119-Ball BGA Pinout (2 Chip Enables with JTAG) CY7C1361C (256K x 36) 1 23 4 5 6 7 A V AA A A V DDQ ADSP DDQ B NC/288M CE A A A NC/512M ADSC 2 C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V V DQ DQ CE C C SS SS B B 1 F V DQ V V DQ V DDQ C SS OE SS B DDQ G DQ DQ ADV DQ DQ BW BW C C B B C B H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ
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CY7C1361C CY7C1363C Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1361C (256K x 36) 1 2 3 4 567 89 10 11 NC/288M CE BW BW CE BWE ADSC ADV A NC A A 1 C B 3 NC/144M A CE BW BW CLK GW OE ADSP A NC/576M B 2 D A C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ V V V V V V V DQ DQ
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CY7C1361C CY7C1363C Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the address locations. Sampled at the rising 0 1 [2] Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled 1 2 3 active. A feed the 2-bit counter. [1:0] BW ,BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the A B BW ,BW Synchronous SRAM. Sampled on the rising edge of CLK. C D GW Input- Global Write
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CY7C1361C CY7C1363C Pin Definitions (continued) Name I/O Description V Ground Ground for the core of the device. SS V I/O Ground Ground for the I/O circuitry. SSQ TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
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CY7C1361C CY7C1363C active, (2) ADSC is asserted LOW, (3) ADSP is deasserted Functional Overview HIGH, and (4) the write input signals (GW, BWE, and BW ) X All synchronous inputs pass through input registers controlled indicate a write access. ADSC is ignored if ADSP is active by the rising edge of the clock. Maximum access delay from LOW. the clock rise (t ) is 6.5 ns (133-MHz device). CDV The addresses presented are loaded into the address register The CY7C1361C/CY7C1363C supports secondary
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CY7C1361C CY7C1363C ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V Comm/ind’l 50 mA DDZZ DD Automotive 60 mA t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ active to sleep current This parameter is sampled 2t ns ZZI CYC t ZZ Inactive to exit sleep current This parameter is sampled 0 ns RZZI [3, 4, 5, 6, 7] Truth Table Address Cycle Description Used CE
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CY7C1361C CY7C1363C [3, 8] Partial Truth Table for Read/Write Function (CY7C1361C) GW BWE BW BW BW BW D C B A Read H H X X X X Read H L HH HH Write Byte (A, DQP)HLHHHL A Write Byte (B, DQP)HLHHLH B Write Bytes (B, A, DQP , DQP)H L H H L L A B Write Byte (C, DQP) H LHLH H C Write Bytes (C, A, DQP , DQP) H LHLH L C A Write Bytes (C, B, DQP , DQP)H L H L L H C B Write Bytes (C, B, A, DQP , DQP , DQP) H L H LLL C B A Write Byte (D, DQP)HLLHHH D Write Bytes (D, A, DQP , DQP)H L L H H L D A Write By
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CY7C1361C CY7C1363C Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1361C/CY7C1363C incorporates a serial boundary and is sampled on the rising edge of TCK. It is allowable to scan test access port (TAP) in the BGA package only. The leave this ball unconnected if the TAP is not used. The ball is TQFP package does not offer this functionality. This part pulled up internally, resulting in a logic HIGH level. oper
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CY7C1361C CY7C1363C TDI and TDO balls as shown in the Tap Controller Block through the instruction register through the TDI and TDO balls. Diagram. Upon power-up, the instruction register is loaded To execute the instruction once it is shifted in, the TAP with the IDCODE instruction. It is also loaded with the IDCODE controller needs to be moved into the Update-IR state. instruction if the controller is placed in a reset state as EXTEST described in the previous section. EXTEST is a mandatory
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CY7C1361C CY7C1363C PRELOAD allows an initial data pattern to be placed at the BYPASS latched parallel outputs of the boundary scan register cells When the BYPASS instruction is loaded in the instruction prior to the selection of another boundary scan test operation. register and the TAP is placed in a Shift-DR state, the bypass The shifting of data for the SAMPLE and PRELOAD phases register is placed between the TDI and TDO balls. The can occur concurrently when required—that is, while data a
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CY7C1361C CY7C1363C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Input timing refere
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CY7C1361C CY7C1363C Scan Register Sizes Register Name Bit Size (x 36) Bit Size (x 18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 71 71 Boundary Scan Order (165-ball FBGA package) 71 71 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TD
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CY7C1361C CY7C1363C 119-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Signal Signal Signal Signal Bit # ball ID Name Bit # ball ID Name Bit # ball ID Name Bit # ball ID Name 1 CLK 37 P4 A0 1 CLK 37 P4 A0 K4 K4 2H4 GW 38 N4 A1 2 H4 GW 38 N4 A1 3M4 BWE 39 R6 A 3 M4 BWE 39 R6 A 4F4 OE 40 T5 A 4 F4 OE 40 T5 A 5B4 ADSC 41 T3 A 5 B4 ADSC 41 T3 A 6A4 ADSP 42 R2 A 6 A4 ADSP 42 R2 A 7 G4 ADV 43 R3 MODE 7 G4 ADV 43 R3 MODE 8C3 A 44 P2 DQP 8 C3 A 44 Internal Internal D 9B3 A
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CY7C1361C CY7C1363C 165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Signal Signal Signal Signal Bit # ball ID Name Bit # ball ID Name Bit # ball ID Name Bit # ball ID Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2B7 GW 38 P6 A1 2 B7 GW 38 P6 A1 3A7 BWE 39 R4 A 3 A7 BWE 39 R4 A 4B8 OE 40 P4 A 4 B8 OE 40 P4 A 5A8 ADSC 41 R3 A 5 A8 ADSC 41 R3 A 6B9 ADSP 42 P3 A 6 B9 ADSP 42 P3 A 7A9 ADV 43 R1 MODE 7 A9 ADV 43 R1 MODE 8B10 A 44 N1 DQP 8 B10 A 44 Internal Internal D 9A10
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CY7C1361C CY7C1363C Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage........................................... >2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current..................................................... >200 mA Storage Temperature ................................–65°C to + 150°C Operating Range Ambient Temperature with Power Applie
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CY7C1361C CY7C1363C [15] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 55 5 pF IN A V = 3.3V DD C Clock Input Capacitance 5 5 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 7 7 pF I/O [15] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 29.41 34.1 16.8 °C/W JA (Junction to Ambient) t
