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CY7C1217H
1-Mbit (32K x 36) Flow-Through Sync SRAM
[1]
Features Functional Description
The CY7C1217H is a 32K x 36 synchronous cache RAM
• 32K x 36 common I/O
designed to interface with high-speed microprocessors with
• 3.3V core power supply (V )
DD
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
• 2.5V/3.3V I/O power supply (V )
DDQ
first address in a burst and increments the address automati-
• Fast clock-to-output ti
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CY7C1217H Logic Block Diagram ADDRESS A0, A1, A REGISTER A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD, DQPD DQD, DQPD BYTE BWD BYTE BYTE WRITE REGISTER WRITE REGISTER WRITE REGISTER DQC, DQPC DQC, DQPC BYTE BWC BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQs MEMORY SENSE BUFFERS DQPA ARRAY DQB, DQPB AMPS DQB, DQPB DQPB BYTE BWB BYTE DQPC WRITE REGISTER WRITE REGISTER DQPD DQA, DQPA DQA, DQPA BYTE BWA BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 RE
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CY7C1217H Pin Configuration 100-Pin TQFP DQP 1 C 80 DQP B DQ 2 C 79 DQ B DQ 3 DQ C 78 B V 4 DDQ 77 V DDQ V 5 V SSQ 76 SSQ DQ 6 C DQ 75 B DQ 7 C DQ 74 B DQ 8 BYTE C 73 DQ BYTE B C B DQ 9 C 72 DQ B V 10 SSQ 71 V SSQ V 11 DDQ 70 V DDQ DQ 12 C 69 DQ B DQ 13 C 68 DQ B NC 14 67 V SS CY7C1217H V 15 NC DD 66 NC 16 65 V DD V 17 ZZ SS 64 DQ 18 DQ D 63 A DQ 19 DQ D 62 A V 20 V DDQ 61 DDQ V 21 60 V SSQ SSQ DQ 22 D 59 DQ A BYTE D BYTE A DQ 23 D 58 DQ A DQ 24 D 57 DQ A DQ 25 D 56 DQ A V 26 SSQ 55 V SSQ V
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CY7C1217H Pin Descriptions Name I/O Description A0, A1, A Input- Address Inputs used to select one of the 32K address locations. Sampled at the rising Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. 1 2 3 A feed the 2-bit counter. [1:0] BW , BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the A B Synchronous SRAM. Sampled on the rising edge of CLK. BW , BW C D GW Input- Global Write Enable Inpu
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CY7C1217H HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) Functional Overview indicate a write access. ADSC is ignored if ADSP is active All synchronous inputs pass through input registers controlled LOW. by the rising edge of the clock. Maximum access delay from The addresses presented are loaded into the address register the clock rise (t ) is 6.5 ns (133-MHz device). CDV and the burst counter/control logic and delivered to the The CY7C1217H supports secondary cache in systems me
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CY7C1217H ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V 40 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ Active to sleep current This parameter is sampled 2t ns ZZI CYC t ZZ Inactive to exit sleep current This parameter is sampled 0 ns RZZI [2, 3, 4, 5, 6] Truth Table Address Cycle Description Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1
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CY7C1217H [2, 3] Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte (A, DQP) H L HHH L A Write Byte (B, DQP)HLHHLH B Write Bytes (B, A, DQP , DQP)H L H H L L A B Write Byte (C, DQP) H LH LH H C Write Bytes (C, A, DQP , DQP) H LH LH L C A Write Bytes (C, B, DQP , DQP)H L H L L H C B Write Bytes (C, B, A, DQP , DQP , DQP) H L H LLL C B A Write Byte (D, DQP) H L L HHH D Write Bytes (D, A, DQP , DQP)H L L H H L D A Write Bytes (D, B, DQP , DQP)H L L
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CY7C1217H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch-up Current.....................................................
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CY7C1217H [9] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V. V = 2.5V DD DDQ C Clock Input Capacitance 5 pF CLK C Input/Output Capacitance 5 pF I/O [9] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods 30.32 °C/W JA (Junction to Ambient) and procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resistan
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CY7C1217H [10, 11] Switching Characteristics Over the Operating Range 133 MHz 100 MHz Parameter Description Min. Max. Min. Max. Unit [12] t V (Typical) to the First Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 2.5 4.0 ns CH t Clock LOW 2.5 4.0 ns CL Output Times t Data Output Valid after CLK Rise 7.5 8.0 ns CDV t Data Output Hold after CLK Rise 2.0 2.0 ns DOH [13, 14, 15] t Clock to Low-Z 00 ns CLZ [13, 14, 15] t Clock to High-Z 3.5 3.5 ns CHZ t OE LOW to Output Val
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CY7C1217H Timing Diagrams [16] Read Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 t t WES WEH GW, BWE,BW [A:D] Deselect Cycle t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst. OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Data Out (Q) High-Z Q(A1) t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 16. On this diagram, when CE is LOW, CE is
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CY7C1217H Timing Diagrams (continued) [16, 17] Write Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC extends burst. t t ADS ADH t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst. t t WES WEH BWE, BW[A:D] t t WEH WES GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst. OE t t DS DH Data in (D) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z D(A1) t OEHZ Data Out (Q) BURST READ Single W
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CY7C1217H Timing Diagrams (continued) [16, 18, 19] Read/Write Timing t CYC CLK t t CL CH t t ADH ADS ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CES CEH CE ADV OE t t DH DS t OELZ High-Z D(A3) D(A5) D(A6) Data In (D) t OEHZ t CDV Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back Back-to-Back READs Single WRITE BURST READ WRITEs DON’T CARE UNDEFINED Notes: 18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or A
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CY7C1217H Timing Diagrams (continued) [20, 21] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05670 Rev. *B Page 14 of 16 [+] Feedback
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CY7C1217H Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 100 CY7C1217H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1217H-100AXI Industrial 133 CY7C1217H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1
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CY7C1217H Document History Page Document Title: CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Document Number: 38-05670 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 345879 See ECN PCI New Data Sheet *A 430677 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added 2.5VI/O option Changed Three-State to Tri-State Included Maximum Ratings for V relative to GND DDQ Modified “Input Load” to “I
