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CY7B9910
CY7B9920
Low Skew Clock Buffer
The completely integrated PLL enables “zero delay” capability.
Features
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
■ All outputs skew <100 ps typical (250 max.)
any factor at the clock destination. This facility minimizes clock
■ 15 to 80 MHz output operation
distribution difficulty while allowing maximum system clock
speed and flexibility.
■ Zero input to output
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CY7B9910 CY7B9920 Pin Configuration SOIC Top View REF 1 24 GND V 2 23 TEST CCQ 22 FS 3 NC NC 21 4 GND V 5 20 CCQ V CCN 6 19 V CCN 7B9910 Q7 7B9920 Q0 18 7 Q6 Q1 8 17 GND 16 GND 9 Q5 15 Q2 10 Q4 11 14 Q3 V CCN V 12 13 FB CCN Pin Definitions Signal Name IO Description REF I Reference frequency input.This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected to one of the eight outputs). [1,2,3] FS I Three level f
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CY7B9910 CY7B9920 Static Discharge Voltage............................................ >2001V Maximum Ratings (MIL-STD-883, Method 3015) Operating outside these boundaries may affect the performance Latch Up Current ..................................................... >200 mA and life of the device. These user guidelines are not tested. Operating Range Storage Temperature .................................–65°C to +150°C Ambient Temperature with Ambient Power Applied ............................
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CY7B9910 CY7B9920 Electrical Characteristics Over the Operating Range CY7B9910 CY7B9920 Parameter Description Test Conditions Min Max Min Max Unit V Output HIGH Voltage V = Min, I = –16 mA 2.4 V OH CC OH V = Min, I =–40 mA V –0.75 CC OH CC V Output LOW Voltage V = Min, I = 46 mA 0.45 V OL CC OL V = Min, I = 46 mA 0.45 CC OL V Input HIGH Voltage 2.0 V V – V V IH CC CC CC (REF and FB inputs only) 1.35 V Input LOW Voltage –0.5 0.8 –0.5 1.35 V IL (REF and FB inputs only) V Three Level Input HIGH Mi
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CY7B9910 CY7B9920 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, V = 5.0V 10 pF IN A CC AC Test Loads and Waveforms 5V 3.0V 2.0V 2.0V R1=130 R1 V =1.5V V =1.5V R2=91 th th 0.8V 0.8V C =50pF(C = 30pF for –5 and – 2 devices) L L C 0.0V L (Includes fixture and probe capacitance) R2 ≤1ns ≤1ns 7B9910–3 7B9910–4 TTL AC Test Load (CY7B9910) TTL Input Test Wavef
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CY7B9910 CY7B9920 CY7B9910–5 CY7B9920–5 Parameter Description Min Typ Max Min Typ Max Unit [1, 2] f Operating Clock FS = LOW 15 30 15 30 MHz NOM Frequency in MHz [1, 2] FS = MID 25 50 25 50 [1, 2, 3] [12] FS = HIGH 40 80 40 80 t REF Pulse Width HIGH 5.0 5.0 ns RPWH t REF Pulse Width LOW 5.0 5.0 ns RPWL [13, 14] t Zero Output Skew (All Outputs) 0.25 0.5 0.25 0.5 ns SKEW [8, 15] t Device-to-Device Skew 1.0 1.0 ns DEV t Propagation Delay, REF Rise to FB Rise –0.5 0.0 +0.5 –0.5 0.0 +0.5 ns PD [16] t
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CY7B9910 CY7B9920 Switching Characteristics [11] Over the Operating Range (continued) CY7B9910–7 CY7B9920–7 Parameter Description Min Typ Max Min Typ Max Unit [1, 2] f Operating Clock FS = LOW 15 30 15 30 MHz NOM Frequency in MHz [1, 2] FS = MID 25 50 25 50 1, 2, 3] [12] FS = HIGH 40 80 40 80 t REF Pulse Width HIGH 5.0 5.0 ns RPWH t REF Pulse Width LOW 5.0 5.0 ns RPWL [13, 14] t Zero Output Skew (All Outputs) 0.3 0.75 0.3 0.75 ns SKEW [8, 15] t Device-to-Device Skew 1.5 1.5 ns DEV t Propagation
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CY7B9910 CY7B9920 AC Timing Diagrams Figure 1. AC Timing Diagrams t t REF RPWL t RPWH REF t PD t ODCV t ODCV FB Q t t JR SKEW t SKEW OTHER Q Figure 2. Zero Skew and Zero Delay Clock Driver REF LOAD Z 0 FB SYSTEM REF CLOCK FS LOAD Q0 Z Q1 0 Q2 Q3 LOAD Q4 Z 0 Q5 Q6 LOAD Q7 TEST Z 0 Document Number: 38-07135 Rev. *B Page 8 of 11 [+] Feedback [+] Feedback
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CY7B9910 CY7B9920 Operational Mode Descriptions Figure 2 shows the device configured as a zero skew clock Figure 1 shows the CY7B9910/9920 connected in series to buffer. In this mode the 7B9910/9920 is used as the basis for a construct a zero skew clock distribution tree between boards. low skew clock distribution tree. The outputs are aligned and may Cascaded clock buffers accumulates low frequency jitter each drive a terminated transmission line to an independent because of the non-ideal filte
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CY7B9910 CY7B9920 Ordering Information Accuracy Operating Ordering Code Package Type (ps) Range 250 CY7B9910–2SC 24-Pb Small Outline IC Commercial CY7B9910–2SCT 24-Pb Small Outline IC - Tape and Reel Commercial [20] CY7B9920–2SC 24-Pb Small Outline IC Commercial 500 CY7B9910–5SC 24-Pb Small Outline IC Commercial CY7B9910–5SCT 24-Pb Small Outline IC - Tape and Reel Commercial CY7B9910–5SI 24-Pb Small Outline IC Industrial CY7B9910–5SIT 24-Pb Small Outline IC - Tape and Reel Industrial CY7B9920–5S
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CY7B9910 CY7B9920 Document History Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer Document Number: 38-07135 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 110244 10/28/01 SZV Change from Specification number: 38-00437 to 38-07135 *A 1199925 See ECN DPF/AESA Added Pb-free parts in Ordering Information Added Note 20: Not recommended for the new design *B 1353343 See ECN AESA Change status to final © Cypress Semiconductor Corporation, 2001-2007.The information contained
