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CY25566
Spread Spectrum Clock Generator
• Center spread modulation
Features
• Low cycle-to cycle jitter
• 25- to 200-MHz operating frequency range
• 16-pin SOIC package
• Wide range of spread selections (9)
Applications
• Accepts clock or crystal inputs
• Provides four clocks
• High-resolution VGA controllers
— SSCLK1a
• LCD panels and monitors
— SSCLK1b
• Printers and MFPs
— SSCLK2
Benefits
—REFOUT
• Peak EMI reduction by 8 to 16 dB
• Low-power dissipation
• Fast time to market
— 3.3V = 70 m
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CY25566 Pin Description Pin Name Type Description 1 XIN/CLKIN I Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. 2REFOFF I Input pin enables REFOUT clock at pin 3. REFOFF 400KΩ internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled. 3REFOUT O Buffered, non-modulated output clock derived from XIN/CLKIN input frequency. There is a 180° phase shift from XIN to REFOUT. 4VDD P Positive power
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CY25566 SSCLK1a/b Control Logic Structures SSCLK1a and SSCLK1b are spread spectrum clock outputs The CY25566 has six input control pins for programming VCO used for the purpose of reducing EMI in digital systems. range, BW %, Mod ON/OFF and REFOUT ON/OFF. These SSCLK1a and SSCLK1b can be connected in several different programmable control pins are described below. ways to provide flexibility in application designs. Each clock can drive separate nets with a capacitative load up to 15 pF REFOFF e
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CY25566 Modulation Rate Spread Spectrum clock generators utilize frequency The CY25566 has three frequency groups to select from. Each modulation (FM) to distribute energy over a specific band of combination of frequency and bandwidth can be selected by frequencies. The maximum frequency of the clock (Fmax) and programming the input control lines, S0–S3, to the proper logic minimum frequency of the clock (Fmin) determine this band of state. frequencies. The time required to transition from Fmin
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CY25566 Table 1. Frequency and Bandwidth Selection Chart (Group 1)(Low Frequency (1x) Selection Chart) 25–50 MHz (Low Range) XIN/CLK S1 = M S1 = M S1 = 1 S1 = 0 S1 = 0 (MHz) S0 = M S0 = 0 S0 = 0 S0 = 0 S0 = M 25–35 4.3 3.8 3.4 2.9 2.8 35–40 3.9 3.5 3.1 2.5 2.4 S3 S2 40–45 3.7 3.3 2.8 2.4 2.3 0 0 45–50 3.4 3.1 2.6 2.2 2.1 50–100 MHz (High Range) XIN/CLK S1 = 1 S1 = 0 S1 = 1 S1 = M (MHz) S0 = M S0 = 1 S0 = 1 S0 = 1 50–60 2.9 2.1 1.5 1.2 60–70 2.8 2.0 1.4 1.1 S3 S2 70–80 2.6 1.8 1.3 1.1 0 0 80
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CY25566 Application Schematic In this example, the CY25566 is being driven by a 75-MHz V = 3.30 VDC. DD reference clock. SSCLK1a = 75 MHz @ 2.5% center spread modulation. S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%. SSCLK1b = 75 MHz @ 2.5% center spread modulation. (Refer to Table 1 and 2.) SSCLK 2 = 37.5 MHz @ 2.5% center spread modulation. S2 = 0 and S3 = 1 are programmed to select the Group 2 REFOUT = 37.5 MHz non-modulated clock. range. VDD 0.1 uF 4 75 MHz Clock source 1 VDD XI
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CY25566 [1, 2] Absolute Maximum Ratings Supply Voltage (V : .......................................................+6V DD Operating Temperature: ......................................0°C to 70°C Storage Temperature ..................................–65°C to +150°C Table 4. DC Electrical Characteristics V = 3.3V, Temp. = 25°C, unless otherwise noted DD Parameter Description Conditions Min. Typ. Max. Unit V Power Supply Range ±10% 2.97 3.3 3.63 V DD V Input High Voltage S0 and S1 only. 0.85V V V
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CY25566 Ordering Information Part Number Package Type Product Flow CY25566SC 16-pin SOIC Commercial, 0° to 70°C CY25566SCT 16-pin SOIC–Tape and Reel Commercial, 0° to 70°C Package Drawing and Dimensions 16-Lead (150-Mil) SOIC S16.15 16 Lead (150 Mil) SOIC PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 0.150[3.810] PACKAGE WEIGHT 0.15gms 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 916 0.010[0.254] X 45° 0.386[9.804] 0.016[0.
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CY25566 Document Title:CY25566 Spread Spectrum Clock Generator Document Number: 38-07429 Issue Orig. of Rev. ECN No. Description of Change Date Change ** 115771 07/01/02 OXC New Data Sheet *A 122705 12/30/02 RBI Added power up requirements to maximum ratings information. *B 404070 See ECN RGL Minor Change: Typo error on table 1, column 2 , S0 = 0 (not M) Document #: 38-07429 Rev. *B Page 9 of 9 [+] Feedback
