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®
Intel IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
®
The Intel IXF1104 is a four-port Gigabit MAC that supports IEEE 802.3 10/100/1000 Mbps
applications. The IXF1104 supports a System Packet Interface Phase 3 (SPI3) system interface
to a network processor or ASIC, and concurrently supports copper and fiber physical layer
devices (PHYs).
The copper PHY interface implements the Gigabit Media Independent Interface (GMII) and the
Reduced Gigabit Media Independent Interfac
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Applications Load Balancing Systems Base Transceiver Station MultiService Switch Serving GRPS Support Node (SGSN) Web Caching Appliances General Packet Radio Services (GGSN) Intelligent Backplane Interfaces Packet Data Serving Note (PDSN) Edge Router Digital Subscriber Line Access Multiplexer (DSLAM) Base Station Controller Cable Modem Termination System Redundant Line Cards (CMTS) ® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENS
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Contents Contents 1.0 Introduction..................................................................................................................................19 1.1 What You Will Find in This Document ................................................................................19 1.2 Related Documents ............................................................................................................19 2.0 General Description .....................................................
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Contents 5.1.5.1 Speed.....................................................................................................77 5.1.5.2 Duplex....................................................................................................77 5.1.5.3 Copper Auto-Negotiation .......................................................................77 5.1.6 Jumbo Packet Support ..........................................................................................77 5.1.6.1 Rx Statistics .........
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Contents 5.6.2.3 Receiver Operational Overview ...........................................................104 5.6.2.4 Selective Power-Down.........................................................................104 5.6.2.5 Receiver Jitter Tolerance .....................................................................104 5.6.2.6 Transmit Jitter ......................................................................................105 5.6.2.7 Receive Jitter .........................................
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Contents 6.0 Applications...............................................................................................................................129 6.1 Change Port Mode Initialization Sequence.......................................................................129 7.0 Electrical Specifications ...........................................................................................................131 7.1 DC Specifications ..............................................................
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Contents 9.2 Package Specifics for the IXF1104...................................................................................223 9.3 Package Information.........................................................................................................224 9.3.1 Example Package Marking ..................................................................................226 10.0 Product Ordering Information .....................................................................................
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Contents 43 MDIO Write Timing Diagram ....................................................................................................145 44 MDIO Read Timing Diagram .................................................................................................... 145 45 Bus Timing Diagram .................................................................................................................146 46 Write Cycle Diagram................................................................
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Contents 33 Mode 1 Clock Cycle to Data Bit Relationship ...........................................................................117 34 LED_DATA# Decodes..............................................................................................................118 35 LED Behavior (Fiber Mode) ......................................................................................................118 36 LED Behavior (Copper Mode) ..................................................................
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Contents 83 Flush TX ($ Port_Index + 0x11)................................................................................................166 84 FC Enable ($ Port_Index + 0x12).............................................................................................167 85 FC Back Pressure Length ($ Port_Index + 0x13).....................................................................167 86 Short Runts Threshold ($ Port_Index + 0x14)............................................................
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Contents 133 TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)............................................203 134 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617) .............................................204 135 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E)..............................................205 136 Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F) ...................................206 137 TX FIFO Port Reset ($0x620)................
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Contents Revision History Revision Number: 007 Revision Date: March 25, 2004 (Sheet 1 of 5) Page # Description All Globally replaced GBIC with Optical Module Interface. All Globally edited signal names. Globally changed SerDes and PLL analog power ball names as follows: TXAVTT and RXAVTT changed to AVDD1P8_2 TXAV25 and RXAV25 changed to AVDD2P5_2 All PLL1_VDDA and PLL2_VDDA changed to AVDD1P8_1 PLL3_VDDA changed to AVDD2P5_1 PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND Reworded and rearra
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Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 2 of 5) Page # Description Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming 38 Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2, “Register Address Conventions”; and added/enhanced material under headings. Added new Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface 57 Multiplexed Balls” and Table 17 “SPI3 MPHY/SPHY Inte
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Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 3 of 5) Page # Description 97 Modified Figure 20 “RX_CTL Behavior” [changed signal names]. Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph, 98 third sentence]. Modified/replaced all text under Section 5.6, “SerDes Interface” on page 102 [added Table 29 102 “SerDes Driver TX Power Levels”]. NA Removed old Section 5.6.2.4 AC/DC Coupling. NA Removed old Section 5.6.2.9 System Jitte
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Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 4 of 5) Page # Description Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”, Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics Registers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”, 155 Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”, Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)
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Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 5 of 5) Page # Description Modified Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)” 206 [renamed heading and bit name]. Modified Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)” 207 [renamed from TX FIFO Number of Frames Removed Ports 3 - 0]. Modified Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)” [renamed 208 from TX FIFO Number of Dropped
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Contents Revision Number: 006 Revision Date: August 21, 2003 (Sheet 2 of 2) Page # Description Modified Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – + 140 0x0C)”. 143 Modified Table 60 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”. 143 Modified Table 61 “Discard Unknown Control Frame Register (Addr: Port_Index + 0x15)”. 143 Modified Table 62 “RX Config Word Register Bit Definition (Addr: Port_Index + 0x16)”. 145 Modified Table 64 “DiverseConfigWrite
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Contents 18 Datasheet Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004
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IXF1104 4-Port Gigabit Ethernet Media Access Controller 1.0 Introduction ® This document contains information on the Intel IXF1104 4-Port 10/100/1000 Mbps Ethernet Media Access Controller (MAC). 1.1 What You Will Find in This Document This document contains the following sections: Section 2.0, “General Description” on page 20 provides the block diagram system architecture. Section 3.0, “Ball Assignments and Ball List Tables” on page 22 shows the signal naming methodology and signal descri
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IXF1104 4-Port Gigabit Ethernet Media Access Controller 2.0 General Description The IXF1104 provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full-duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network processor is supported through a System Packet Interface Phase 3 (SPI3) media interface. The following PHY interfaces are selected on a per-port basis: Serializer/Deserializer (SerDes) with Optical Module Interface support Gigab
