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MZ-700
SHARP SERVICE MANUAL
-r' ............................................................. ..
CODE: OOZMZ700SMI/E
PERSONAL COMPUTER
MODEL MZ-700
MZ-1TOl
MZ-1POl
(FOR THE MZ-lPOI MECHANICAL SECTION
REFER TO THE DPG2306 SERVICE MANUAL)
INDEX
1. SPECIFICATIONS. . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . .. . . .. . . .. 1
2. NAMES OF FUNCTIONAL COMPONENTS. . . . . . . . . . . . . . . . . . . .. 2
3. SYSTEM BLOCK DIAGRAM .............................. _ .. 3
4. SYSTEM
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~\~Z~ 700 1. SPECIFICATION 1-1. MZ-700 1-3. Micro-colour graphics printer specification (option) Sharp LH0080A (Z-80A) Printing method Ball point pen recording, four colours CPU 3.5MHz rotary selection type. Oock(ct» Memory 4KB ROM (monitor) Kind of colours I = black, 2 = blue, 3 = green, 4= red 4KB ROM (character generator) Printing speed 10 characters/sec, average (Printing the 64KB RAM (program area) smallest characters.) 4KB RAM (VIDEO) Printing capacity 80 digits, 40 digits, 26 d
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MZ-700 2. NAME OF FUNCTIONAL COMPONENT MZ-700 Front view plolter prioter recorder (cassette) INS. DEL key ":::d'---,----CUrSOI control keV$ Main kev board -----' MZ-700 Aeer view BrN-Colour switch Channel switch Composi! terminal . socket plOHtr printer Dat8 recorder Reset switch RF terminal !c3S$IIttll) AGe terminal Volume CantUI! re<:order jKk EKt. output terminal Adiust Joy nick ulfminal Ext. printer F,.me ground terminal termmal 1
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~"q-700 3. SYSTEM BLOCK DIAGRAM CRT ( F.G A.C. sw 100V t t I~ -"" 0- !II w MEMORY CONTRa. R.G.B. I I 5V ~PO~UP' a:: Cl VIDEO RAM llER (CRTC) PLY CIRCUIT p :Ja:: -.., I I ,.-- 00 Fi ...JU RF I I ~ oz _J I -uw ~~ ~ I VIDEO CHAR a:: RESET 1 ...J eJ Reset .... I GEN c( CIRCUITJ ~ sw ~ MAIN MEMORY 64KB DRAM MONITOR ROM i- Z80A ,...... CPU III IT A \ \ ADDRESS BUS I -y en :J III n A I n= Q. " \ ~dJA - I a: - X " " .. ft H rn. t\.0 t .
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4. SYSTEM DESCRIPTION • Boot command: L 4-1. Memory map • With the entry of the boot command L, only the tape a) At power on loading program is transferred to the system area and the $0000 $0000 SYSTEM (DRAM) MONITOR system program is loaded to the system area designated and (ROM) TEXT AREA in the DRAM. $1000 $1000 MONITOR WORK NOTE: The boot program shown in the figure is the $1200 program loaded from the tape and is not the SYSTEM program from the monitor (ROM). and TEX
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~1Z -7CO At the time of manual reset (with I CTRL I in depression) a. 8 x 8 dot characters are displayed on the CRT screen of 40 characters (horizontal) x 25 lines (vertical). Displayed $0000 $0000 character font is dependent on the 4KB character MONITOR - SYSTEM (ROM) generator (ROM). ~ $1000 $1000 b. Manages the monitor ROM, DRAM, video RAM, and peripherals (keyboard, timer, ETC.) mapped to the memory. SYSTEM c. Generates clock to the Z-80A microprocessor. d. Selects the printe
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To read the contents of a VRAM character, the CPU The signal that determines the function (shift LOAD: sends out the relevant address. When RD is forced low, the out or data set) of the shift register LS165. data is then read via the bidirectional buffer LS245. High state of this signal acts as shift and low However, the address range $0000 through $DFFF must state of this signal acts as data set. be addressed in order to access all the VRAM. This address CLK: Shift register clock. Data shi
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\ ,'1Z -700 2) Memory controller • Custom LSI internal memory controller block diagram and description In the MZ· 700, it needs to segregate the memory in order When the above mentioned OUT command is executed, to acheive the above mentioned memory mapping. The is therefore used to perform address address Ao ,.., A2 is stored in "FF" to create INHl ,.., memory controller management of peripherals assigned to the memory such INH3, then ROM, VRAM, and DRAM may be accessed as DRAM, monito
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IV? 7ce 4-4. Memory controller (CRTC) circuit description The memory controller and the CRTC are contained in the single chip custom LSI (M60719). Memory controller signal description & Circuit diagram Function Pin No. Signal name IN/OUT signal name CPU address Bus AO 1 AO l l IN l A15 16 A15 IN Clock (17.7MHz) 17 LPH1 cp IN CPU clock (3.55MHz) 18 PHI 8255, 8253, joystick enable 19 CSEN OUT CSE IN GND 10 CL CL GATE IN GND GATE 21 Monitor ROM enable 22 CSON OUT CSO
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CUSTOM LSI < YTl > 1. BLOCK DIAGRAM CRT Control J I LPHI 1/2 - 0 CLKN ~ ~ I COLR - HSY ~ r-- NTSC H. SYNC. (NTSC) BLNK 1/2 l-{ PAL J ~ r-- SELECT "V HBLN I-- IMT BLNK0 I.....- H. SYNC. (PAL) f---- AND I 1/4 Eh H COLR ~ LOO ..., - ~ LOAD NTPL 0 A-C SCREEN POSITION (1) PO 3 ~ \. , P1 ~ "U P2 a: w P3 X ~ w P4 ..J ABC ~ 0.. P5 i= ~ 8 ..J P6 D-K \ ::> SCREEN ~ r-- , ::i: P7 POSITION (2) Cl) Y Cl) P8 V w a: pg 0 ~ 0 I' 5 P1
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Memory Management (1) • ,... IORN " AND PRCN -0 A1 0 A2 0 ~ A3 0 A4 0 A5 0 ." AS 0 BLNK ..... A7 " 3 2 -" " \. , " AO 0 Z 0 '---- ~
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Memory Management (2) PH111 ~------------------------------<1SEL CAS circuit WRN MRQN RDN COLR NTSC ~-------------In PH 10 PAL 1/4 LPH1 select NTPL CL 0 GATE 0 VCC 0 GND 0 4-3. Memory mapped I/O ($EOOO - $EOO8) Colour VRAM (VRAM-2) • MZ-700 colour infonnation is managed character by character. One byte of colour infonnation table is assign CPU memory Controller Function ed to each characters displayed on the TV screen. address $EOOO PA : Output $EOOl Pe : Input D
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a) Signals around the 8255 The 8255 Programmable Peripehral I/O Controller assumes blinking timing, keyboard scan strobe output, and key the control of the cassette recorder, CRT screen cursor return data. 8255 r--- PBO Key data \ 0, input terminal 0, PB7 (8P) \ Do '- VBLNK PC7 5560UT PC6 AI AI INTMSK PC2 PC5 Ao RDATA MOTOR PC4 Cassette control M·ON RD PC3 WDATA PCl WR CS PA7 556RST 8255 RESET RESET 0 LS Key data 0 PA, strobe terminal 145 C (lOP) PA. -
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1-o1 .. _--464~-__ ... II.oo ... _-49 .• 4j.1S----I .. -+oI ..... 240~-'-264~'" , I "I I I I , ;.' ______ _ I CASE1 LONG -----.... -- SHORT U 368j.1S 368j.1S --J ' READ READ READ READ POINT EDGE POINT EDGE t (Rising edge SHORT starts sampling (HIGH) 240lls counter) (LOW) 264lls LONG (HIGH) 464lls (LOW) 494j.1S READ POINT 368lls "LONG" is the data written for the bit value of" 1" and as a repetition of LONG and SHORT, with the same data "SHORT" for the bit value of "0". Data is r
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c) Keyboard controDer The 8255 writes strobe (key scan signals) on PA and reads key data from PB. The table shown below is the key map. d) Signals around the 8253 The 8253 Programmable Timer generates the buzzer tone 8253 through the counter #(J and keeps the internal timer function via the counters #1 and #2. OUT2+----TO CPU INT The counter #(J is used as a square waveform generator (Mode 3). The counter #1 is used as a rate generator (Mode 2) and #2 as an interrupt upon terminal cou
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5. DATA RECORDER 5-1. Data recorder (MZ-lT01) • Cassette specification Data transfer with the recorder is carried out via the 8255. Method PWM recording method The read data is sent out through the port Cl and the Rated power 5V ± O.25V write data is received through the port C5. The motor on/off control is carried out via the port C3 and that Wait: 2mA Rated current Record: 210mA (TEAC TEST TAPE) activation of the motor is confmned through the port C4. Playback: 150mA (TEAC TEST TAPE
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I iv1Z 700 Troubleshooting procedure Phenomennon CD: Motor and tape do not rotate, when the PLAY button is pushed. Motor fai lure Check if the SW302 interlinked with the Check if M+ Check +5V on REMOTE terminal @. P LAY push button is and M·5V are NO in supply. active. Check the +5V input OV: when SW is on voltage. Check R3009. +5V: when SW is off OK Check the motor lead wire (REM) and the motor transistor (2S0468) Check if voltage is on to the base of the remote control tra
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Mechanical adjustments RECORD/FAST FORWARDjREWIND torque measure Tape speed adjustment ments 1. Connect the wow-flutter measuring instrument to :f#!, 1. Set the torque measuring instrument on the cassette pin of the CNW3001 connector. tape recorder. 2. Playback the test tape (UKOG-0119CSZZ, MTT-1l3 2. Torque value under each mode must be as follows: recorded with 8KHz signals). Use the middle part of the tape for the test. 3. Adjust the semi-fix~ resistor located on the Motor Torque mea
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MZ~700 Cassette recorder waveforms Primary stage amplifier output wavefonn Operational amplifier input wavefonn Operational amplifier input wavefonn ® CD ® 1. 1.8V /1 IJ 6mv~ vpp pp AWl ov T ~ r Operational amplifier input wavefonn Operational amplifier output wavefonn Output wavefonn @ ® ® f1 " " Tt T T 1.SVpp 4Vpp sVpp 1 \lV""~'" 1 1 Recording input wavefonn Recording signal amplified wavefonn Recording signal amplified wavefonn (J) ® ® ~ ~ ~ r - - - T~ T- T O
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~\;1Z 700 5-2. External recorder playback circuit • 8-Pin DIN connector When the external recorder is used, connection is made with the 8255 by shorting P-12. In this condition, the I VIDEO write data (8255 PC output) is differentiated and sent 2 GND to the recorder. In the case of read, the signal peak is '5' VSYNC chopped by DI and D2 (about O.6V), amplified in the 4 HSYNC 7~~ 3 • 1.2V limiter (about 1.2V), then amplified to 5V in the '3' CSYNC next stage amplifier. The phase of th
