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rate to support applications such as digital telephone
Introduction
answering machine (TAM) and voice annotation.
The Rockwell RS56-PCI (SoftK56) Host Software
SP models support position independent, full-duplex
Processed V.90/K56flex Modem Device Family supports
speakerphone (FDSP).
high speed analog data, 14.4 kbps fax, voice/TAM, and
Fax Group 3 send and receive rates are supported up to
speakerpho
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV Supports PCI Bus Power Management • Features (Continued) - Conforms to PCI Bus Power Management • System compatibilities Specification, Rev. 1.1 Windows 95, Windows 95 OSR2, Windows 98, - ACPI Power Management Registers - Windows NT 4.0, Windows NT 5.0 operating systems - PME# and APM support Microsoft's PC 98 Design Initiative compliant - Device packages: • - Unimodem/V compliant - BIF and LVC i
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, RS56-PCI SINGLE DEVICE TELEPHONE LINE COMBINED PCI BUS TELEPHONE LINE/ PCI BUS INTERFACE AND LINE/VOICE HANDSET (OPTIONAL) TELEPHONE HANDSET/ CODEC [TAM AND SP MODELS] MIC AND SPEAKER (LVC) INTERFACE CIRCUIT [R6793; SPEAKER (OPTIONAL) 144-PIN TQFP] MIC (OPTIONAL) [SP MODELS] SOUND CARDS OR DEVICE(S) SPEAKER (OPTIONAL) PCI BUS AND AUDIO INTERFACE CIRCUIT MIC (OPTIONAL) [OPTIONAL FOR SPEAKERPHONE OPER
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV and reception performed by the modem are controlled and Description monitored through the fax EIA/IA-578 Class 1 and T.31 Class 1.0 command interface. Full HDLC formatting, zero General insertion/deletion, and CRC generation/checking are The RS56-PCI Device Sets provide the processing core provided. for a complete system design featuring data/fax modem, Synchronous Access Mode (SAM) - Video voice/TAM,
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, Hardware Interface Signals The major functional interface signals are shown in Figure 2. Bus Interface and Codec (BIC) Interface The BIC (R6793) 144-pin TQFP hardware interface signals are shown in Figure 3. The BIC (R6793) 144-pin TQFP pin assignments are shown in Figure 4. Bus Interface (BIF) Interface The BIF (11235) 176-pin TQFP hardware interface signals are shown in Figure 5. The BIF (11235) 176
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 28.224 MHZ XIN CRYSTAL XOUT CIRCUIT CLKRUN# GND THRU 1K VIO OH# (GPIO0) PCICLK CID# (GPIO1) PCIRESET# VOICE# (GPIO2) FRAME# RINGWAKE# (INPUT0) IDSEL RS56-PCI CID_DATA (INPUT1) DEVSEL# SINGLE DEVICE MODEM LCS# (INPUT2) IRDY# [R6793: 144-PIN TQFP] IRING# (INPUT3) TRDY# DAA AND EXT_L# (INPUT4) PAR TELEPHONE LCS_L#/RH_L# (INPUT5) REQ# OR INTERFACE RXA GNT# PCI BUS TXA1 INTA# 2-DEVICE MODEM TXA2 STOP# OF
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, VCC D1 BAS16 R12 10K +3.3V U3 PCIPME# 85 119 SROMCS 1 5 PCIPME# PME# SROMCS CS GND 1 122 SROMCLK 2 6 VIO1 SROMCLK SK PE 140 121 SROMIN 3 7 VI/O VIO2 SROMIN DI PRE 120 SROMOUT 4 8 EEPROMVCC SROMOUT DO VDD 114 R10 1k VAUX INPUT7/VauxDET 117 104 OH# 93LC46B/SN GPOH1/VpciEN OH#/GPIO0 OH# 116 103 GPOH0/VauxEN CID#/GPIO1 125 102 VpciDET VOICE#/GPIO2 118 101 GPOL1 GPIO3 100 SPEAKMUTE GPIO8 SPEAKMUTE PCICLK 1
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 * PIN IS NC ON R6793-12 ONLY (RS56-PCI) MD231F4 PO-R6793-144T Figure 4. BIC (R6793: 144-Pin TQFP) Pin Signals 0’ VIO1 VDD AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# VDD PAR CBE1# AD15 AD14 VDD AD13 AD12 AD11 AD10 VDD AD9 AD8 CBE0# VDD GND AD7 108
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, 158 SPKMUTE (GPIO8) AUDIO CIRCUIT 27pF 167 5% OH# (GPIO0) 132 166 XIN CID# (GPIO1) 165 VOICE# (GPIO2) 170 28.224 MHz 1M RINGWAKE# (INPUT0) 171 CID_DATA (INPUT1) DAA 131 172 XOUT LCS# (INPUT2) 173 IRING# (INPUT3) 27pF 174 5% EXT_L# (INPUT4) 27 175 PCICLK LCS_L#/RH_L# (INPUT5) 62 FRAME# 46 113 IDSEL M_CS# 66 135 DEVSEL# M_IRQ 63 106 IRDY# M_TXCLK 64 105 TRDY# M_TX 86 108 LVC CBE0# M_RXCLK 73 136 (OPTI
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 * SIGNAL NOT SUPPORTED BY SOFTK56 MODEM. CONNECT PIN AS DESCRIBED FOR FOR RH56-PCI (RC56HCF-PCI) PIN-COMPATIBLE DESIGNS. MD231F6-11235 PO-176TQFP Figure 6. BIF (11235: 176-Pin TQFP) Pin Signals 0’ 132 VDD INPUT6 131 130 VauxDET 129 GND VDD 128 127 VauxEN# VpciEN# 126 125 G
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, 33 140 128 BIF: OSC_OUT NC (CLKIN) NC (CELL_BUSY) 141 127 NC (XTLI) NC NC NC (CELL_CLOCK) 143 78 NC (XTLO) NC NC (CELL_DATA) 67 BIF: M_CS# NC (CS#) 130 BIF: M_IRQ GND (IRQ) 11 20 BIF: DA0 NC (RS0) TELIN 12 22 BIF: DA1 NC (RS1) TELOUT 64 30 BIF: DA2 NC (RS2) RXA DAA 65 25 BIF: DA3 NC (RS3) TXA1 66 26 BIF: DA4 NC (RS4) TXA2 144 28 BIF: DD0 NC (D0) VC 1 27 BIF: DD1 NC (D1) VREF 3 BIF: DD2 NC (D2) 4 BIF:
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NOTE: SIGNALS IN PARENTHESES SHOW CORRESPONDING RC56HCF-PCI SIGNALS IF DIFFERENT FROM SOFTK56-PCI SIGNALS. MD231F8 20410PO-144T Figure 8. LVC (20410: 144-Pin TQFP) Pin Signals 0’ NC (D1) NC (GP14) NC (D2) NC (D3) NC (GP11) NC (D4) NC (SYCLK) NC (D5) NC (D6) NC (D7) NC (RS0) NC (RS1) NC
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, 2 SPKMD 19 3 MCLKIN BIF: M_CLK SPKOUT AUDIO CIRCUIT 20 14 BIF: M_TXSIN MTXSIN MIC_M 22 BIF: M_RXOUT MRXOUT 23 MSTROBE BIF: M_STROBE BIF 21 13 BIF: M_SCLK MSCLK RXA 18 9 BIF: M_CTRL MCTRLSIN TXA1 DAA 1 10 BIF: SLEEP IASLEEP TXA2 4 12 RESET# LINE BIF: DRESET# VC 11 VREF CODEC 26 NC (VAA = +5V) OR SET3V# (LC) 0.1 CER 10 AGND (VAA = +3.3V) 32-TQFP 17 [20437] 15 +3.3V AVDD MICBIAS NC 0.1 CER 25 24 10 +3.3V
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV Figure 11. Package Dimensions - 176-Pin TQFP 0’
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, D D1 D2 PIN 1 REF D1 D D1 D2 e b DETAIL A Millimeters Inches* Dim. Min. Max. Min. Max. A 1.6 MAX 0.0630 MAX A1 0.05 0.15 0.0020 0.0059 D1 A2 1.4 REF 0.0551 REF D 21.75 22.25 0.8563 0.8760 D1 20.0 REF 0.7874 REF D2 17.5 REF 0.6890 REF L 0.5 0.75 0.0197 0.0295 L1 1.0 REF 0.0394 REF e 0.50 BSC 0.0197 BSC b 0.17 0.27 0.0067 0.0106 A2 A c 0.11 0
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV D D1 D2 PIN 1 REF D1 D D1 D2 e b DETAIL A Millimeters Inches* Dim. Min. Max. Min. Max. A 1.6 MAX 0.0630 MAX A1 0.05 0.15 0.0020 0.0059 D1 A2 1.4 REF 0.0551 REF D 8.75 9.25 0.3445 0.3642 D1 7.0 REF 0.2756 REF D2 5.6 REF 0.2205 REF L 0.5 0.75 0.0197 0.0295 L1 1.0 REF 0.0394 REF e 0.80 BSC 0.0315 BSC b 0.30 0.40 0.0118 0.0157 A2 A c 0.13 0.19 0
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, Table 2. Current and Power Requirements Conditions Current Power Device State (Dx) PCI Bus PCI Clock Line Typical Maximum Typical Maximum and Bus State (Bx) Power (PCICLK) Connection Current (mA) Current (mA) Power (mW) Power (mW) Single Device (R6793-12 BIC) and 2-Device Set (11235-14 BIF and 20437-11 LC) D0, B0 On Running Yes 33 36 109 130 D0, B0 On Running No 22 24 73 86 D3, B0 On Running No 22 24
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6RIW.3&, +RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV Table 3. Absolute Maximum Ratings Parameter Symbol Limits Units Supply Voltage V -0.5 to +4.0 V DD Input Voltage V -0.5 to (VDD +0.5) (BIF) V IN -0.5 to (VGG +0.5)* (LVC) Operating Temperature Range T -0 to +70 °C A Storage Temperature Range T -55 to +125 °C STG Analog Inputs V -0.3 to (VAA + 0.5) V IN Voltage Applied to Outputs in High Impedance (Off) State V -0.5 to (VDD +0.5) (BIF) V HZ -0.5 to (VG
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+RVW6RIWZDUH3URFHVVHG9 .IOH[ 0RGHP'HYLFH)DPLO\IRU'HVNWRS$SSOLFDWLRQV 6RIW.3&, NOTES Information provided by Rockwell International Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Rockwell International for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Rockwell International other than for circuitry
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