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S1D13505 Embedded RAMDAC LCD/CRT Controller
S1D13505
TECHNICAL MANUAL
Document Number: X23A-Q-001-12
Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accura
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Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics. To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representa
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ENERGY SAVING EPSON GRAPHICS S1D13505 S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER October 2001 DESCRIPTION The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation. The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a nu
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GRAPHICS S1D13505 SYSTEM BLOCK DIAGRAM EDO-DRAM FPM-DRAM Analog Out Data and CPU S1D13505 Control Signals CRT Digital Out Flat Panel CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13505 Technical Linux Console Driver Manual S5U13505 Evaluation Boards Windows CE Display Driver TM CPU Independent Software VXWorks Tornado Display Utilities Driver Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology & T
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S1D13505 Embedded RAMDAC LCD/CRT Controller Hardware Functional Specification Document Number: X23A-A-001-14 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document ar
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Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Overview Description . . . . . . . . . . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1.1 SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
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Epson Research and Development Page 5 Vancouver Design Center 8.2.5 Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.2.6 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.2.7 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.2.8 Look-Up Table Reg
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Epson Research and Development Page 7 Vancouver Design Center List of Tables Table 5-1: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5-2: Memory Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5-2: LCD Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 8 Epson Research and Development Vancouver Design Center Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . .85 Table 7-28: 16-Bit Single Color Passive LCD Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . .87 Table 7-29: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . .89 Table 7-30: 8-Bit Dual Color Passiv
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Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram (SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3-2: Typical System Diagram (SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000) . . . . . . . . . . . . . . . . . . . . . 16 Figure 3-4
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Page 10 Epson Research and Development Vancouver Design Center Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1). . . . . . . . . . . . . . . . . . . . . 82 Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . 83 Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2). . . . . . . . . . . . . . . . . . . . . 84 Figure 7-33: 8-Bit Single Color Passive LCD
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Epson Research and Development Page 11 Vancouver Design Center 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13505 Embedded RAMDAC LCD/CRT Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This specification will be updated as appropriate. Please check the Epson Electr
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Page 12 Epson Research and Development Vancouver Design Center 2 Features 2.1 Memory Interface 16-bit DRAM interface: EDO-DRAM up to 40MHz data rate (80M bytes/sec.). FPM-DRAM up to 25MHz data rate (50M bytes/sec.). Memory size options: 512K bytes using one 256K ×16 device. 2M bytes using one 1M ×16 device. Performance Enhancement Register to tailor the memory control output timing for the DRAM device. 2.2 CPU Interface Supports the following interfaces: 8/16-bit SH-4 bus i
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Epson Research and Development Page 13 Vancouver Design Center 2.3 Display Support 4/8-bit monochrome passive LCD interface. 4/8/16-bit color passive LCD interface. Single-panel, single-drive displays. Dual-panel, dual-drive displays. Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth (16-bit data). Embedded RAMDAC (DAC)with direct analog CRT drive. Simultaneous display of CRT and passive or TFT/D-TFD panels. 2.4 Display Modes 1/2/4/8/15
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Page 14 Epson Research and Development Vancouver Design Center 2.7 Miscellaneous The memory data bus, MD[15:0], is used to configure the chip at power-on. Three General Purpose Input/Output pins, GPIO[3:1], are available if the upper Memory Address pins are not required for asymmetric DRAM support. Suspend power save mode can be initiated by either hardware or software. The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be use
