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32-Bit RISC MICROPROCESSOR
TX39 FAMILY CORE ARCHITECTURE
USER'S MANUAL
Jul. 27, 1995
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Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No result from its use. No or others. The products described in this document contain components made in the United States and subject to export control of the U.S.authorities. Diversion contrary to the U.S. law is prohibited. use these TOSHIBA products in equipments which require high quality and/or reliability, and i
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CONTENTS CONTENTS Architecture Chapter 1 Introduction -------------------------------- -------------------------------- ----------- 3 1.1 -------------------------------- -------------------------------- -------------- 3 -------------------------------- -------------------- 3 r embedded applications -------------------------------- ------------------- 3 -------------------------------- -------------------------------- --- 4 ---------- 4 1.2 Notation Used in This Manual --------------------
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CONTENTS Chapter 4 Pipeline Architecture -------------------------------- -------------------------------- - 4.1 Overview -------------------------------- -------------------------------- ---------------- 4.2 -------------------------------- -------------------------------- --------------- Delayed load -------------------------------- -------------------------------- ------------------- -------------------------------- -------------------------------- ------------ 4.3 Nonblocking Load Function -
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CONTENTS -------------------------------- ------------------------ -------------------------------- -------------------------------- ------------------------ Overflow exception -------------------------------- -------------------------------- ----------- -------------------------------- ---------------------------- -------------------------------- -------------------------------- --------------- System Call exception -------------------------------- -------------------------------- ------- -----
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CONTENTS TMPR3901F Chapter 1 Introduction -------------------------------- -------------------------------- ----------- 1.1 -------------------------------- -------------------------------- -------------- 1.2 Internal Blocks -------------------------------- -------------------------------- ------- Chapter 2 Configuration -------------------------------- -------------------------------- -------- R3900 Processor Core -------------------------------- ---------------------------- -------------------
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CONTENTS 4.5 Bus Arbitration -------------------------------- -------------------------------- ------- -------------------------------- -------------------------------- - -------------------------------- -------------------------------- ------------------ -------------------------------- -------------------------------- ------------------ Half-Speed Bus Mode -------------------------------- ----------------------------- -------------------------------- -------------------------------- - Halt mo
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Architecture Architecture 1
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Architecture 2
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Architecture Chapter 1 Introduction The R3900 Processor Core is a high-performance 32-bit microprocessor core developed by Toshiba based on The R3000A was developed by and provides the R3900 as a processor core in Embedded Array or Cell-based ICs. The low power consumption and high cost-performance ratio of this processor make it especially well-suited to embedded control 1 • - instructions and some coprocessor instructions) - • - Separate instruction and data caches - Data cache snoop f
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Architecture • - • - - • 1 • Power Down mode - Prepare for Reduced Frequency mode: Control the clock frequency of the R3900 Processor Core - Halt and Doze mode: Stop R3900 Processor Core operations • Clock can be stopped - Clock signal can be stopped at high state 1 • • Easy-to-design peripheral circuits - Single direction separate bus: Bus configuration suitable for core - Built-in cache memory: No need to consider cache operation timing • • 4 Sufficient Development Environment ASIC Pr
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Architecture Notation Used in This Manual Mathematical notation • Hexadecimal numbers are expressed as follows (example shown for decimal number 42) 0x2A 10 20 • A K(kilo)byte is 2 = 1,024 bytes, a M(mega)byte is 2 = 1,024 x 1,024 = 1,048,576 bytes, and a 30 G(giga)byte is 2 = 1,024 x 1,024 x 1,024 = 1,073,741,824 bytes. • Byte: 8 bits • Halfword: 2 contiguous bytes (16 bits) • Word: 4 contiguous bytes (32 bits) • Doubleword: 8 contiguous bytes (64 bits) Signal notation • Low active signals are
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Architecture 2. 6
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Architecture Chapter 2 Architecture Overview A block diagram of the R3900 Processor Core is shown in Figure 2-1. It includes the CPU core, an instruction cache and a data cache. You can select an optimum data and instruction cache configuration for The CPU Core comprises the following blocks: • : C). • : Registers for system control coprocessor (CP0) functions. • : • : • Bus interface unit : Control bus interface between CPU core and external circuit. • : Direct Figure 2-1. Block Diag
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Architecture 2.2 CPU registers The R3900 Processor Core has the following 32-bit registers. • Thirty-two general-purpose registers • A program counter (PC) • HI/LO registers for storing the result of multiply and divide operations The configuration of the registers is shown in Figure 2-2. Multiply/Divide registers General-purpose registers 31 0 31 0 r0 HI r1 31 0 r2 LO . . . . Program counter r29 31 0 PC r30 r31 Figure 2-2. R3900 Processor Core registers The r0 and r31 registers have special f
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Architecture 2 System control coprocessor (CP0) registers The R3900 Processor Core can be connected to as many as three coprocessors, referred to as CP1, The Figure 2-3 shows the functional breakdown of the CP0 Status register Cause register EPC register BadVAddr register PRld register † Config register † † Additional R3900 Processor Core Cache register registers not present in the R3000A † † Debug register DEPC register Figure 2-3 CP0 registers 9 registe
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Architecture Table 2-1 lists the CP0 registers built into the R3900 Processor Core. Some of these registers are reserved Table 2-1. List of system control coprocessor (CP0) registers No Mnemonic Description † - (reserved) 0 † - (reserved) 1 † - (reserved) 2 †† Config 3 † - (reserved) 4 † - (reserved) 5 † - (reserved) 6 †† 7 Last virtual address triggering error 8 † - (reserved) 9 † - (reserved) † - (reserved) Processor revision ID ††† ††† DEPC † - (reserved) | † †† Addit
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Architecture Instruction Set Overview All R3900 Processor Core instructions are 32 bits in length. There (I-type), jump (J-type) and register (R-type), as shown in Figure 2-4. Having just three instruction formats If more complex functions or addressing modes are required, they can be produced with the compiler using combinations of the instructions. I-type (Immediate) 31 26 25 21 20 16 15 0 op rs rt immediate J-type (Jump) 31 26 25 0 op target 31 26 25 21 20 16 15 11 10 6 5 0 op rs rt rd sa
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Architecture The instruction set is classified as follows. (1) All instructions in this group are I-type. “ ” is the only supported addressing mode. (2) The be R-type (when both operands and the result are register values) or I-type (when one operand is 16- (3) These instructions change the program flow. A jump is always made to a 32 bit address contained in a register (R-type format ), or to a paged absolute address constructed by combining a 26-bit target address with the upper 4 bits of
