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Title Page
PPC440x5 CPU Core
User’s Manual
Preliminary
SA14-2613-02
September 12, 2002
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User’s Manual Preliminary PPC440x5 CPU Core Contents Figures ............................................................................................................................ 15 Tables .............................................................................................................................. 19 About This Book ............................................................................................................ 23 1. Overview ..................................
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User’s Manual PPC440x5 CPU Core Preliminary 2.3.2 Allocated Instruction Class ..................................................................................................... 54 2.3.3 Preserved Instruction Class ................................................................................................... 55 2.3.4 Reserved Instruction Class .................................................................................................... 56 2.4 Implemented Instruction Set Summary ...
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User’s Manual Preliminary PPC440x5 CPU Core 2.10 Synchronization ............................................................................................................................. 82 2.10.1 Context Synchronization ...................................................................................................... 82 2.10.2 Execution Synchronization .................................................................................................. 83 2.10.3 Storage Ordering and Synchr
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User’s Manual PPC440x5 CPU Core Preliminary 5.1 MMU Overview .............................................................................................................................. 133 5.1.1 Support for PowerPC Book-E MMU Architecture ................................................................ 133 5.2 Translation Lookaside Buffer ......................................................................................................... 134 5.3 Page Identification ......................
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User’s Manual Preliminary PPC440x5 CPU Core 6.4.4 Critical Save/Restore Register 0 (CSRR0) .......................................................................... 168 6.4.5 Critical Save/Restore Register 1 (CSRR1) .......................................................................... 168 6.4.6 Machine Check Save/Restore Register 0 (MCSRR0) ......................................................... 169 6.4.7 Machine Check Save/Restore Register 1 (MCSRR1) ....................................
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User’s Manual PPC440x5 CPU Core Preliminary 7.4 Watchdog Timer ............................................................................................................................ 213 7.5 Timer Control Register (TCR) ....................................................................................................... 215 7.6 Timer Status Register (TSR) ......................................................................................................... 216 7.7 Freezing the Timer Fa
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User’s Manual Preliminary PPC440x5 CPU Core 9.3 Pseudocode .................................................................................................................................. 251 9.3.1 Operator Precedence .......................................................................................................... 253 9.4 Register Usage ............................................................................................................................. 253 9.5 Alphabetical Ins
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User’s Manual PPC440x5 CPU Core Preliminary icbt ............................................................................................................................................. 314 iccci............................................................................................................................................ 316 icread......................................................................................................................................... 317 isel ..
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User’s Manual Preliminary PPC440x5 CPU Core mtspr ......................................................................................................................................... 370 mulchw ...................................................................................................................................... 373 mulchwu .................................................................................................................................... 374 mulhhw...........
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User’s Manual PPC440x5 CPU Core Preliminary stwu ........................................................................................................................................... 426 stwux ......................................................................................................................................... 427 stwx ........................................................................................................................................... 428 subf......
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User’s Manual Preliminary PPC440x5 CPU Core ICDBDR..................................................................................................................................... 491 ICDBTRH .................................................................................................................................. 492 ICDBTRL................................................................................................................................... 493 INV0–INV3 ................
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User’s Manual PPC440x5 CPU Core Preliminary Index ............................................................................................................................. 571 Revision Log ................................................................................................................ 589 ppc440x5TOC.fm. Page 14 of 583 September 12, 2002
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User’s Manual Preliminary PPC440x5 CPU Core Figures Figure 1-1. PPC440 Core Block Diagram .................................................................................................30 Figure 2-1. User Programming Model Registers ......................................................................................48 Figure 2-2. Supervisor Programming Model Registers ............................................................................49 Figure 2-3. Link Register (LR) ...............
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User’s Manual PPC440x5 CPU Core Preliminary Figure 6-3. Save/Restore Register 1 (SRR1) .........................................................................................168 Figure 6-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................168 Figure 6-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................169 Figure 6-6. Machine Check Save/Restore Register 0 (MCSRR
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User’s Manual Preliminary PPC440x5 CPU Core Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) .............................................................479 Figure 10-15. Data Exception Address Register (DEAR) ...........................................................................480 Figure 10-16. Decrementer (DEC) .............................................................................................................481 Figure 10-17. Decrementer Auto-Reload (DECAR) ..........
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User’s Manual PPC440x5 CPU Core Preliminary Figure A-2. B Instruction Format .............................................................................................................522 Figure A-3. SC Instruction Format ...........................................................................................................522 Figure A-4. D Instruction Format .............................................................................................................522 Figure A-5. X Instr
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User’s Manual Preliminary PPC440x5 CPU Core Tables Table 2-1. Data Operand Definitions .......................................................................................................40 Table 2-2. Alignment Effects for Storage Access Instructions ................................................................40 Table 2-3. Register Categories ...............................................................................................................50 Table 2-4. Instruction Categories
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User’s Manual PPC440x5 CPU Core Preliminary Table 5-4. Access Control Applied to Cache Management Instructions ...............................................144 Table 6-1. Interrupt Types Associated with each IVOR .........................................................................171 Table 6-2. Interrupt and Exception Types ..............................................................................................175 Table 7-1. Fixed Interval Timer Period Selection ....................
