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TMS320C6455/C6454 DSP
DDR2 Memory Controller
User 's Guide
Literature Number: SPRU970G
December 2005 –Revised June 2011
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2 SPRU970G –December 2005 –Revised June 2011 Submit Documentation Feedback Copyright © 2005 –2011, Texas Instruments Incorporated
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Contents Preface ....................................................................................................................................... 7 1 Introduction ........................................................................................................................ 9 1.1 Purpose of the Peripheral .............................................................................................. 9 1.2 Features ...................................................................
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www.ti.com List of Figures 1 Device Block Diagram .................................................................................................... 10 2 DDR2 Memory Controller Signals....................................................................................... 12 3 DDR2 MRS and EMRS Command...................................................................................... 14 4 Refresh Command ........................................................................................
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www.ti.com List of Tables 1 DDR2 Memory Controller Signal Descriptions......................................................................... 12 2 DDR2 SDRAM Commands .............................................................................................. 13 3 Truth Table for DDR2 SDRAM Commands............................................................................ 13 4 Addressable Memory Ranges ........................................................................................
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6 List of Tables SPRU970G –December 2005 –Revised June 2011 Submit Documentation Feedback Copyright © 2005 –2011, Texas Instruments Incorporated
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Preface SPRU970G –December 2005 –Revised June 2011 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signal processors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangl
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8 Read This First SPRU970G –December 2005 –Revised June 2011 Submit Documentation Feedback Copyright © 2005 –2011, Texas Instruments Incorporated
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User 's Guide SPRU970G –December 2005 –Revised June 2011 C6455/C6454 DDR2 Memory Controller 1 Introduction 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage. 1.2 Features The DDR2 memory controller supports the following features: • JESD79-2B stan
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Introduction www.ti.com Figure 1. Device Block Diagram L1P cache/SRAM EMIFA L2 memory L1 program memory controller Advanced controller event Cache control triggering Bandwidth management Cache (AET) DDR2 memory control Memory protection controller Bandwidth management C64x+ CPU Memory Instruction fetch PLL2 IDMA protection SPLOOP buffer 16/32−bit instruction dispatch Instruction decode Data path A Data path B External memory L1 S1 M1 D1 D2 M2 S2 L2 controller Configuration Register file A Regist
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www.ti.com Peripheral Architecture 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters. The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform r
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Peripheral Architecture www.ti.com Figure 2. DDR2 Memory Controller Signals DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DDR2 DSDDQM[3:0] Memory DSDDQS[3:0] Controller DSDDQS[3:0] DBA[2:0] DEA[13:0] DED[31:0] DEODT[1:0] DSDDQGATE[3:0] V REFSSTL DDRSLRATE Table 1. DDR2 Memory Controller Signal Descriptions Pin Description DED[31:0] Bidirectional data bus. Input for data reads and output for data writes. DEA[13:0] External address output. DCE0 Active-low chip enable for memory space CE0.
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www.ti.com Peripheral Architecture 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. Deactivates (precharges) a single bank. DESEL Device Deselect. EMRS Extended Mode Register set. Allows alteri
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Peripheral Architecture www.ti.com 2.4.1 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on DBA[1:0] selects the mode register to
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www.ti.com Peripheral Architecture 2.4.2 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC). Page information is always invalid before and after a REFR
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Peripheral Architecture www.ti.com 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DBA[2:0] selects the bank and the value of A[12:0] selects the row. When the DDR2 memory controller issues an ACTV command, a delay of t is incurred before a RCD read or write command is issued. Fi
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www.ti.com Peripheral Architecture 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command, DEA10 is driven high to ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command. Figure 6. DCAB Command DCAB DDR2CLKOUT DDR2C
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Peripheral Architecture www.ti.com The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows the timings diagram for a DEAC command. Figure 7. DEAC Command DEAC DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDRAS DSDCAS DSDWE DEA[13:11, 9:0] DEA[10] DBA[2:0] DSDDQM[3:0] 18 C6455/C6454 DDR2 Memory Controller SPRU970G –December 2005 –Revised June 2011 Submit Documentation Feedback Copyright © 2005 –2011, Texas Instruments Incorporated
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www.ti.com Peripheral Architecture 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DSDCAS drives low, DSDWE and DSDRAS remain high, the column address is driven on DEA[12:0], and the bank address is driven on DBA[2:0]. The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or 5. The CAS latency is three cyc
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Peripheral Architecture www.ti.com 2.4.6 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. The use of the DSDDQM outputs allows byte and halfword writes to be executed. Figure 9 shows the timing for a write on the DDR2 memory controller. If the transfer request is for less than 8 words, depending on the s
