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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
Low-Price/High-Performance Floating-Point
16-Bit External Memory Interface (EMIF)
Digital Signal Processor (DSP):
− Glueless Interface to Asynchronous
TMS320C6712D
Memories: SRAM and EPROM
− Eight 32-Bit Instructions/Cycle
− Glueless Interface to Synchronous
− 150-MHz Clock Rate
Memories: SDRAM and SBSRAM
− 6.7-ns Instruction Cycle Time
− 256M-Byte Total Addressable External
− 900 M
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 EMIF big endian mode correctness . . . . . . . . . . . . . . . . 60 GDP and ZDP BGA package (bottom view) . . . . . . . . . . . . . 5 bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 description . . . . . . . . . . . . . . . . . . . . . . . . . .
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 REVISION HISTORY The TMS320C6712D device-specific documentation has been split from TMS320C6712, TMS320C6712C, TMS320C6712D Floating−Point Digital Signal Processors, literature number SPRS148L, into a separate Data Sheet, literature number SPRS293. It also highlights technical changes made to SPRS293 to generate SPRS293A; these changes are marked by “[Revision A]” in the Revision History table
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PAGE(S) ADDITIONS/CHANGES/DELETIONS NO. 83 RESET TIMING section: Added Note 88 MULTICHANNEL BUFFERED SERIAL PORT TIMING: switching characteristics over recommended operating conditions for McBSP section: Updated McBSP Timings figure for clarification 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 GDP and ZDP BGA package (bottom view) GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) Y W V U T R P N M L K J H G F E D C B A 1 3 57 9 11 13 15 17 19 2468 10 12 14 16 18 20 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 description † The TMS320C67x DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices ) are members of the floating-point DSP family in the TMS320C6000 DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichanne
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 device characteristics Table 1 provides an overview of the DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C6000 DSP device part numbers and part numbering, see Figure 5. Table 1. Characteristics of the C6712D Processor INTERNAL CLOCK C6712D HARDWAR
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 device compatibility The TMS320C6712 and C6211/C6711 devices are pin-compatible; thus, making new system designs easier and providing faster time to market. The following list summarizes the device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, C6711D, C6712, C6712C, and C6712D devices: The C6211 and C6211B devices have a fixed-point TMS320C62x DSP core (CPU), whi
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 functional block and CPU (DSP core) diagram Digital Signal Processor SDRAM External SBSRAM 16 Memory L1P Cache Interface Direct Mapped SRAM (EMIF) 4K Bytes Total ROM/FLASH Timer 0 I/O Devices C67x CPU (DSP Core) Timer 1 Instruction Fetch Control L2 Registers Instruction Dispatch Memory Enhanced Control 4 Banks Multichannel Instruction Decode DMA Logic 64K Bytes Buffered Controller Data Path A D
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description (continued) src1 ÁÁÁÁ Á Á ÁÁÁÁ Á † src2 .L1 ÁÁÁÁ Á ÁÁ dst ÁÁÁÁ Á Á 8 long dst 8 ÁÁÁÁ Á long src 32 LD1 32 MSB ÁÁÁÁ Á Á ST1 32 Register ÁÁÁÁ Á long src File A 8 long dst ÁÁÁÁ Á (A0−A15) 8 Data Path A dst † ÁÁÁÁ .S1 Á src1 ÁÁÁÁ Á Á src2 ÁÁÁÁ ÁÁÁÁ Á Á dst ÁÁÁÁ Á Á † src1 .M1 ÁÁÁÁ ÁÁ Á src2 ÁÁÁÁ Á Á Á LD1 32 LSB ÁÁÁÁ dst ÁÁ src1 .D1 Á ÁÁÁÁ Á DA1 src2 2X Á ÁÁÁÁ Á 1X src2 Á
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 memory map summary Table 2 shows the memory map address ranges of the device. Internal memory is always located at address 0 and can be used as both program and data memory. The configuration registers for the common peripherals are located at the same hex address ranges. The external memory address ranges in the device begin at the address location 0x8000 0000. Table 2. Memory Map Summary MEMO
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions Table 3 through Table 13 identify the peripheral registers for the device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature num
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 5. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Selects which interrupts drive CPU interrupts 10−15 019C 0000 MUXH Interrupt multiplexer high (INT10−INT15) Selects which interrupts drive CPU interrupts 4−9 019C 0004 MUXL Interrupt multiplexer low (INT04−INT09) Sets the polarity of the external interrupts 019C 00
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2. 31 0 EDMA Parameter Word 0 EDMA Channel Options Parameter (OPT) OPT Word 1 EDMA Channel Source Address (SRC) SRC Word 2 Array/Frame Count (FRMCNT) Element Count (ELECNT) CNT Word 3 EDMA Channel Destination Address (DST) DST Word 4 Array/Frame Index (FRMIDX) Elem
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 10. PLL Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheral identification register (PID) [0x00010801 for PLL Controller] 01B7 C004 − 01B7 C0FF − Reserved 01B7 C100 PLLCSR PLL control/status register 01B7 C104 − 01B7 C10F − Reserved 01B7 C110 PLLM PLL multiplier control register 01B7 C114 PLLDIV0 PLL controll
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 12. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE ACRONYM ACRONYM REGISTER NAME REGISTER NAME COMMENTS COMMENTS TIMER 0 TIMER 1 Determines the operating mode of the timer, monitors the 0194 0000 0198 0000 CTLx Timer x control register timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to co
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description CLKIN RESET NMI ‡ CLKOUT3 EXT_INT7 Reset and ‡ EXT_INT6 Interrupts † CLKOUT2 ‡ EXT_INT5 Clock/PLL ‡ EXT_INT4 CLKMODE0 LENDIAN PLLHV BIG/LITTLE § ENDIAN EMIFBE TMS RSV TDO RSV TDI • TCK IEEE Standard Reserved TRST • 1149.1 EMU0 • (JTAG) RSV EMU1 Emulation EMU2 RSV EMU3 EMU4 BOOTMODE1 EMU5 BOOTMODE BOOTMODE0 Control/Status 16 ED[15:0] Data ECLKIN ECLKOUT Memory ARE/SDCAS
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) TOUT1 TOUT0 Timer 1 Timer 0 TINP1 TINP0 Timers McBSP1 McBSP0 CLKX1 CLKX0 FSX1 Transmit Transmit FSX0 DX1 DX0 CLKR1 CLKR0 FSR1 FSR0 Receive Receive † DR1 DR0 † CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5) GP[4](EXT_INT4) GPIO CLKOUT2/GP[2] General-Purpose Input/Output (GPIO) Port † For pro
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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS On the device, bootmode and certain device configurations/peripheral selections are determined at device reset. Other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. device configurations at device reset Table 14 describes the device configurati
