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Intel IXP45X and Intel IXP46X
Product Line of Network Processors
Hardware Design Guidelines
February 2007
Document No:305261; Revision:004
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have
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® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors Contents 1.0 Introduction ..............................................................................................................9 1.1 Content Overview................................................................................................9 1.2 Related Documentation...................................................................................... 10 1.3 Acronyms and Abbreviations....................
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 3.12.1 Signal Interface......................................................................................48 3.12.2 PCI Interface Block Diagram.....................................................................49 3.12.3 Supporting 5 V PCI Interface....................................................................50 3.12.4 PCI Option Interface......................................................................
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® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 7.1.7.1 Clock Group ............................................................................. 88 7.1.7.2 Data, Command, and Control Groups........................................... 89 7.2 Simulation Results............................................................................................. 90 7.2.1 Clock Group........................................................................................... 90 7
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 44 DDR RAS Simulation Results: Two-Bank x16 Devices ....................................................99 45 DDR Command (MA3) Topology: Two-Bank x16 Devices..............................................101 46 DDR Address Simulation Results: Two-Bank x16 Devices .............................................102 47 DDR Command (RAS) Topology: Two-Bank x16 Devices ..............................................103 48 DDR
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® ® Revision History—Intel IXP45X and Intel IXP46X Product Line of Network Processors Revision History Date Revision Description • Section 1.4, Figure 1, Figure 2, Section 3.5: Updated the number of supported SMII ports from six to three. • Table 11, Table 12, Table 16: Updated pin type for UTP_OP_ADDR[4:0], UTP_IP_ADDR[4:0], and ETH_MDC. • Section 7.0, “DDR-SDRAM” : Updated design information. February 2007 004 • Removed SS-SMII references since this feature is not supported. • Incorporated
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Revision History ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors HDD February 2007 8 Document Number: 305261, Revision: 004
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® ® Introduction—Intel IXP45X and Intel IXP46X Product Line of Network Processors 1.0 Introduction This design guide provides recommendations for hardware and system designers who ® ® are developing with the Intel IXP45X and Intel IXP46X Product Line of Network ® Processors. This document should be used in conjunction with the Intel IXP45X and ® Intel IXP46X Product Line of Network Processors Datasheet and sample schematics ® provided for the Intel IXDP465 Development Platform in that platf
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Introduction 1.2 Related Documentation The reader of this design guide should also be familiar with the material and concepts presented in the following documents: Title Document # ® Hardware-Assisted IEEE 1588* Implementation in the Intel IXP46X 305068 Product Line White Paper ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors 306262 Developer’s Manual ® ® Intel IXP45X and Intel IXP46X Product Line of N
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® ® Introduction—Intel IXP45X and Intel IXP46X Product Line of Network Processors 1.3 Acronyms and Abbreviations Table 1 lists the acronyms and abbreviations used in this guide. Table 1. List of Acronyms and Abbreviations Term Explanation AHB Advanced High-Performance Bus APB Advanced Peripheral Bus ATM Asynchronous Transfer Mode DDR Double Data Rate EMI Electro-Magnetic Interference GPIO General Purpose Input/Output HSS High Speed Serial I2C Inter-Integrated Circuit IP Internet Protocol ISA In
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Introduction • 32-bit PCI interface Master/Target 33/66 MHz • Device Universal Serial Bus (USB) Controller • Host Universal Serial Bus (USB) Controller • DDRI-266 SDRAM (133-MHz Clock, 266-Mbps per data line) — User-enabled ECC, supports up to 1 Gbyte of external memory • 32-bit Expansion Bus Interface — Master/Target interface •Two UART ports • Up to three Ethernet ports (consult device part number for enabled features) MII/
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® ® Introduction—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® Figure 1. Intel IXP465 Component Block Diagram HSS 0 HSS 1 NPE A UTOPIA 2/MII/SMII MII/SMII NPE B NPE C North AHB 133.32 MHz x 32 bits MII/SMII AES/DES/SHA/ MD-5 North AHB Arbiter IEEE 1588 2 I C Cryptography SSP Unit Queue AHB/AHB DDRI Memory Manager Bridge USB Device Hardware RNG Controller Unit Version 1.1 Hashing SHA1 Exponentiation Unit 32 Bit + ECC UART 0 921 KBaud AHB Slave/ APB
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Introduction 1.5 Typical Applications • High-performance DSL modem • High-performance cable modem •Residential gateway •SME router • Integrated access device (IAD) •Set-top box • DSLAM • Access points — 802.11a/b/g • Industrial controllers • Network printers •VoIP Gateways ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors HDD December 2006 14 Document Number: 305261; Revision: 004
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® ® System Architecture—Intel IXP45X and Intel IXP46X Product Line of Network Processors 2.0 System Architecture 2.1 System Architecture Description ® ® The Intel IXP45X and Intel IXP46X Product Line of Network Processors are multi- ® function processors that integrate the Intel XScale Processor (ARM* architecture compliant) with highly integrated peripheral controllers and intelligent network processor engines. The processor is a highly integrated design, manufactured with Intel’s 0.18-micro
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PCI Slots SDRAM Memory Bus cPCI J1 cPCI J2 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—System Architecture ® Figure 2. Intel IXP465 Example System Block Diagram JTAG Header DDR DDR Flash CB[7:0] DDR SDRAM SDRAM 32 Mbyte SDRAM 16Mx4x16 D[31:0] DDR CS_N0 16Mx4x16 16Mx4x16 512 Mbyte SDRAM BA[1:0] 512 Mbyte 512 Mbyte (Four Chips) Max 1 Gbyte (Four Chips) D[31:0] A[13:0] (Four Chips) RAS, CAS, WE, CS,CLK Board A[24:0] Configuration Reset Logic ® HSS 1 SLIC/CODEC or Intel IXP
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® ® General Hardware Design Considerations—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3.0 General Hardware Design Considerations This chapter contains information for implementing and interfacing to major hardware ® ® blocks of the Intel IXP45X and Intel IXP46X Product Line of Network Processors. Such blocks include DDR SDRAM, Flash, SRAM, Ethernet PHYs, UART and most other peripherals interfaces. Signal definition tables list resistor recommendations for pull- ups and
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—General Hardware Design Considerations Table 3. Soft Fusible Features Name Description PCI The complete bus must be enabled or disable. HSS0/1 Can only be disable as a pair. If enabling UTOPIA, MACs on NPE A are disabled. UTOPIA If enabling MACs on NPE A, UTOPIA are disabled. Can Enable either MII MACs or SMII MACs, but not both at the same time. Enable of MACs ETHERNET can be separately done per each NPE. USB Host Each USB c
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® ® General Hardware Design Considerations—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 4. DDR SDRAM Interface Pin Description (Sheet 2 of 2) Input VTT Name Outpu Device-Pin Connection Terminatio Description t n The WE signal must be connected Write Strobe — Defines whether or not the DDRI_WE_N O to each device in a daisy chain Yes current operation by the DDR SDRAM is to be manner a read or a write. Data Bus Mask — Controls the DDR SDRAM data input buffers. Assert
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® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—General Hardware Design Considerations 3.2.2 DDR SDRAM Memory Interface The IXP45X/IXP46X network processors support compatible DDR-266 SDRAM, 8- and 16-bit wide devices, with a total bus width of 32 bits. Only 32-bit-wide accesses are supported. The maximum supported memory is 1 Gbyte, configured by enabling both physical banks of DDR-266 SDRAM devices. Each bank can be composed of four 1-Gbit (32 Mbit X 8 X 4) devices an
