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Intel Xeon Processor E3-1200 v3
Product Family
Datasheet – Volume 1 of 2
June 2013
Order No.: 328907-001
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHA
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Contents—Processor Contents Revision History..................................................................................................................8 1.0 Introduction................................................................................................................. 9 1.1 Supported Technologies.........................................................................................10 1.2 Interfaces............................................................................
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Processor—Contents 4.2 Processor Core Power Management......................................................................... 50 ® ® 4.2.1 Enhanced Intel SpeedStep Technology Key Features..................................50 4.2.2 Low-Power Idle States...............................................................................51 4.2.3 Requesting Low-Power Idle States...............................................................52 4.2.4 Core C-State Rules.....................................
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Contents—Processor 6.14 Processor Internal Pull-Up / Pull-Down Terminations................................................ 85 7.0 Electrical Specifications.............................................................................................. 86 7.1 Integrated Voltage Regulator..................................................................................86 7.2 Power and Ground Lands ...................................................................................... 86 7.3 V Voltag
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Processor—Contents Tables 1 Terminology........................................................................................................... 12 2 Related Documents..................................................................................................15 3 Processor DIMM Support by Product...........................................................................18 4 Supported UDIMM Module Configurations....................................................................18 5 PCI E
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Contents—Processor 53 Processor Storage Specifications..............................................................................104 54 Processor Ball List by Signal Name........................................................................... 106 ® ® Intel Xeon Processor E3-1200 v3 Product Family June 2013 Datasheet – Volume 1 of 2 Order No.: 328907-001 7
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Processor—Revision History Revision History Revision Description Date 001 • Initial Release June 2013 ® ® Intel Xeon Processor E3-1200 v3 Product Family Datasheet – Volume 1 of 2 June 2013 8 Order No.: 328907-001
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Introduction—Processor 1.0 Introduction ® ® The Intel Xeon processor E3-1200 v3 product family are 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform consisting of a processor and ® Platform Controller Hub (PCH). The processors are designed to be used with the Intel C220 Series chipset. See the following figure for an example platform block diagram. ® ® Note: Throughout this document, the Intel Xeon processor E3-1200 v3 pro
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Processor—Introduction Figure 1. Platform Block Diagram 1333 / 1600 MT/s PCI Express* 3.0 2 DIMMs / CH CH A Processor Digital Display System Memory CH B Interface (DDI) (3 interfaces) Note: 2 DIMMs / CH is not supported on all SKUs. ® Intel Flexible Display Direct Media Interface 2.0 ® Interface (Intel FDI) (DMI 2.0) (x4) (x2) USB 3.0 Analog Display (up to 6 Ports) (VGA) USB 2.0 Integrated LAN (8 Ports) Platform Controller Hub (PCH) SATA, 6 GB/s PCI Express* 2.0 (up to 6 P
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Introduction—Processor ® ® • Intel Advanced Encryption Standard New Instructions (Intel AES-NI) • PCLMULQDQ Instruction ® • Intel Secure Key ® ® • Intel Transactional Synchronization Extensions (Intel TSX) • PAIR – Power Aware Interrupt Routing • SMEP – Supervisor Mode Execution Protection Note: The availability of the features may vary between processor SKUs. 1.2 Interfaces The processor supports the following interfaces: • DDR3/DDR3L • Direct Media Interface (DMI) • Digital Display Interface (
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Processor—Introduction 1.4 Thermal Management Support • Digital Thermal Sensor • Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Open and Closed Loop Throttling • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS 1.5 Package Support The processor socket type is noted as LGA 1150. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1150). See the appropriate Pr
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Introduction—Processor Term Description eDP Embedded Display Port EPG Electrical Power Gating EU Execution Unit FMA Floating-point fused Multiply Add instructions FSC Fan Speed Control HDCP High-bandwidth Digital Content Protection HDMI* High Definition Multimedia Interface HFM High Frequency Mode iDCT Inverse Discrete IHS Integrated Heat Spreader GFX Graphics GUI Graphical User Interface IMC Integrated Memory Controller ® Intel 64 64-bit memory extensions to the IA-32 architecture Technology ®
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Processor—Introduction Term Description Non-Critical to Function. NCTF locations are typically redundant ground or non-critical NCTF reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. ODT On-Die Termination OLTM Open Loop Thermal Management Platform Compatibility Guide (PCG) (previously known as FMB) provides a design PCG target for meeting all planned processor frequency requirements. Platform Controller Hub. The chi
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Introduction—Processor Term Description T is a static value that is below the TCC activation temperature and used as a CONTROL T trigger point for fan speed control. When DTS > T , the processor must comply CONTROL CONTROL to the TTV thermal profile. Thermal Design Power: Thermal solution should be designed to dissipate this target TDP power level. TDP is not the maximum power that the processor can dissipate. TLB Translation Look-aside Buffer Thermal Test Vehicle. A mechanically equivalent pack
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Processor—Introduction Document Document Number / Location http:// Advanced Configuration and Power Interface 3.0 www.acpi.info/ http:// PCI Local Bus Specification 3.0 www.pcisig.com/ specifications http:// PCI Express Base Specification, Revision 2.0 www.pcisig.com http:// DDR3 SDRAM Specification www.jedec.org DisplayPort* Specification http://www.vesa.org http:// www.intel.com/ ® Intel 64 and IA-32 Architectures Software Developer's Manuals products/processor/ manuals/index.htm ® ® Intel Xeo
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Interfaces—Processor 2.0 Interfaces 2.1 System Memory Interface • Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM) with a maximum of two DIMMs per channel. • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • Memory data transfer rates of 1333 MT/s and 1600 MT/s • 64-bit wide channels • DDR3/DDR3L I/O Voltage of 1.5 V for Intel AMT Server, and Workstation • DDR3L I/O voltage of 1.35 V for Rack/Micro
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Processor—Interfaces 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependent on the PCH SKU in the target platform. Note: The IMC supports a maximum of two DDR3/DDR3L DIMMs per channel; thus, allowing up to four device ranks per channel. Note: The support of DDR3/DDR3L frequencies and number of DIMMs per chann
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Interfaces—Processor Raw DIMM DRAM DRAM # of # of # of # of Page Size Card Capacity Device Organization DRAM Physical Row / Col Banks Version Technology Devices Devices Address Inside Ranks Bits DRAM A 1 GB 1 Gb 128 M X 8 8 1 14/10 8 8K 2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K B 4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K 8 GB 4 Gb 512 M X 8 16 2 16/10 8 8K Server and Workstation Platforms Unbuffered / ECC Supported DIMM Module Configurations 1 GB 1 Gb 128 M X 8 9 1 14/10 8
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Processor—Interfaces ® Dual-Channel Mode – Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into symmetric and asymmetric zones. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached. In this mode, the system runs with one zone of dual-channel mode and one zone of single-channel mode, simultaneously, acros
