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Intel 31154 133 MHz PCI Bridge
Design Guide
Design Guide
April 2004
Order Number: 278944-001
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® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may hav
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Contents Contents 1 About This Document ......................................................................................................................7 1.1 Terminology and Definitions .................................................................................................7 2 Introduction......................................................................................................................................9 2.1 Product Overview ......................................
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Contents 7.2.4.2 PICMG 1.2 System Overview ................................................................52 8 Power Considerations ...................................................................................................................57 8.1 Analog Power Pins ............................................................................................................. 57 8.2 Power Sequencing..............................................................................................
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Contents 9 Secondary Bus Frequency Initialization......................................................................................33 10 PCI-X Initialization Pattern..........................................................................................................34 ® 11 Intel 31154 133 MHz PCI Bridge Decoupling Recommendations ............................................38 12 Add-in Card Routing Parameters...............................................................................
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Contents Revision History Date Revision Description April 2004 001 Initial release ® 6 Intel 31154 133 MHz PCI Bridge Design Guide
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About This Document About This Document 1 This document provides layout information and guidelines for designing platform or add-in board ® applications with the Intel 31154 133 MHz PCI Bridge. This document is intended to be used as a guideline only. Intel recommends that you employ best- known design practices with board-level simulation, signal-integrity testing, and validation for a robust design. Please note that this design guide focuses on specific design considerations for the 31154
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About This Document Table 1. Terminology and Definition (Sheet 2 of 2) Term Definition An aggressor network is a network that transmits a coupled signal to another network. Zo Zo Aggressor Victim Network Zo Zo Aggressor Network B3337-01 A network that receives a coupled cross-talk signal from another network is a called the victim Victim network. A network is the trace of a PCB that completes an electrical connection between two or more Network components. Stub A stub is a branch from a trunk
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Introduction Introduction 2 2.1 Product Overview ® The Intel 31154 133 MHz PCI Bridge (called hereafter the “31154”) is a PCI component that functions as a highly concurrent, low-latency transparent bridge between two PCI buses. The 31154 can operate as a PCI-to-PCI bridge in the configurations shown in Table 2. Table 2. PCI-to-PCI Bridge Configurations Primary Bus Interface Secondary Bus Interface PCI 2.3 PCI 2.3 PCI 2.3 PCI-X PCI-X PCI 2.3 PCI-X PCI-X The 31154 is used on motherboards to pro
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Introduction The 31154 has additional hardware support for CompactPCI* Hot Swap and Redundant System Slot via queue flush, arbiter lock, and clock output tristating. The 31154 supports any combination of 32-bit and 64-bit data transfers on its primary and secondary bus interfaces. The 31154 is 33/66 MHz capable in conventional PCI mode, and can run at 66 MHz, 100 MHz, or 133 MHz when operating in PCI-X mode, depending upon its surrounding environment. 2.2 Features List Table 3. Features List
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Introduction 2.3 Related External Specifications PCI Local Bus Specification, Revision 2.3 PCI-to-PCI Bridge Architecture Specification, Revision 1.1 PCI Bus Power Management Interface Specification, Revision 1.1 Compact PCI Hot Swap Specification, Revision 2.1 R2.0 PCI-X Addendum to the PCI Local Bus Specification, Revision 1.1 Embedded PCI-X Specification PICMG 1.2 R1.0 2.4 References This section lists references that can be useful with a 31154 application. These documents are av
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Introduction THIS PAGE INTENTIONALLY LEFT BLANK ® 12 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
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Package Information Package Information 3 ® The Intel 31154 133 MHz PCI Bridge is offered in a 421-lead PBGA package. The mechanical dimensions for this package are provided in Figure 2 on page 14. Figure 3 on page 15 and Figure 4 on page 16 show the 421-lead PBGA, mapped by pin function. These figures are helpful in placing components around the 31154 for the layout of a PCB. To simplify routing and minimize the number of cross traces, keep this layout in mind when placing components on yo
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Package Information ® Figure 2. Intel 31154 133 MHz PCI Bridge Package Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. PIN #1 Dimension is measured at the maximum solder ball 0.90 Ø CORNER 2 diameter, parallel to primary datum 0.60 22 20 18 16 14 12 10 8 6 4 2 2 23 21 19 17 15 13 11 9 7 5 3 1 Primary datum and seating plane are defined by the Ø 0.30 S C A S B S A 3 B spherical crowns of the solder balls. 1.27 C D 4. All dimensions, unless otherwise specified, are in millimet
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Package Information ® Figure 3. Intel 31154 133 MHz PCI Bridge Ball Map—Top View, Left Side 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 P_ P_ P_ P_ P_ P_ VSS VSS VCCP VSS VSS VCCP A A ACK64# AD56 AD60 CBE4# CBE7# PAR64 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ VSS B B AD43 AD54 SERR# AD49 AD50 AD52 AD55 AD57 AD59 AD63 CBE6# SCAN_ P_ P_ S_CLK P_ P_ P_ P_ P_ P_ VSS VCCP C C EN AD48 STOP# OEN3 AD53 PERR# AD58 AD61 CBE5# REQ64# S_CLK P_ P_ P_ QE VSS VCCP VCCP VSS VCC VCC VSS D D OEN2 AD47 AD51 AD62
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Package Information ® Figure 4. Intel 31154 133 MHz PCI Bridge Ball Map—Top View, Right Side 13 14 15 16 17 18 19 20 21 22 23 P_ P_ P_ P_ P_ P_ P_ VSS VSS VCCP VSS A CBE0# CBE3# IRDY# FRAME# AD04 AD07 VCCA P_ P_ P_ P_ P_ P_ P_ P_ P_ VSS TDO B AD00 AD02 TRDY# AD05 AD08 CBE1# IDSEL AD15 REQ# P_ P_ P_ P_ P_ P_ P_ MT0# VSS TDI TRST# C AD01 AD03 AD06 AD09 PAR AD10 GNT# P_ P_ P_DEV P_ VCC VCC VSS VCCP VCCP VSS TMS D CBE2# AD11 SEL# AD22 HS_ NT_ P_ P_ P_ VSS GPIO0 GPIO1 VSS GPIO2 VCCP E FREQ1 MASK# CLK
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Package Information 3.1 Total Signal Count Table 4. Total Signal Count Interface Signals PCI bus interface 112 PCI 64-bit extensions 78 Clock and reset 20 JTAG 12 Serial ROM interface 4 CompactPCI* Hot Swap 6 Hardware strap 5 Miscellaneous 17 Total 254 § § ® Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 17
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Package Information THIS PAGE INTENTIONALLY LEFT BLANK ® 18 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
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Terminations Terminations 4 ® This chapter details all the recommended Intel 31154 133 MHz PCI Bridge terminations required for the different operating modes. The chapter provides the recommended pull-up and pull-down terminations for a 31154 layout. Table 5 lists these 31154 termination values. Note that for motherboards, the PCI Local Bus Specification, Revision 2.3 requires that the PCI signals provide the termination resistors. Table 5. Pull-Up/Pull-Down Terminations (Sheet 1 of 9) Signal
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Terminations Table 5. Pull-Up/Pull-Down Terminations (Sheet 2 of 9) Signal Pull-Up/Pull-Down or Termination (See Note 1) Comments P_GNT# Connect to GNT# of the primary PCI bus. Connect to one of the AD lines of the primary PCI Refer to Section 5.3, “IDSEL Lines” on page 30 for P_IDSEL# bus or to the IDSEL# signal of the PCI edge more details. connector (for add-in card applications). Connect to the M66EN signal of the primary PCI P_M66EN bus of the PCI add-in card finger. P_PAR Connect to PA
