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CY8C24123
CY8C24223, CY8C24423
®
PSoC Programmable System-on-Chip™
■ Additional System Resources
Features
2
❐ I C ™ Slave, Master, and Multi-Master to 400 kHz
■ Powerful Harvard Architecture Processor
❐ Watchdog and Sleep Timers
❐ M8C Processor Speeds to 24 MHz
❐ User-Configurable Low Voltage Detection
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Integrated Supervisory Circuit
❐ Low Power at High Speed
❐ On-Chip Precision Voltage Reference
❐ 3.0 to 5.25 V Operating Voltage
■ Complete Development Tools
❐
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Row Output Configuration Digital Clocks From Core CY8C24123 CY8C24223, CY8C24423 ® Digital System PSoC Functional Overview The Digital System is composed of four digital PSoC blocks. ® The PSoC family consists of many Mixed Signal Array with Each block is an 8-bit resource that can be used alone or On-Chip Controller devices. These devices are designed to combined with other blocks to form 8, 16, 24, and 32-bit replace multiple traditional MCU-based system components with peripherals, which ar
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CY8C24123 CY8C24223, CY8C24423 Figure 2. Analog System Block Diagram Analog System The Analog System is composed of six configurable blocks, each P0[7] P0[6] comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can P0[5] P0[4] be customized to support specific application requirements. Some of the more common PSoC analog functions (most P0[3] P0[2] available as user modules) are: P0[1] P0[0] ■ Analog-to-digital converters
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CY8C24123 CY8C24223, CY8C24423 Additional System Resources Getting Started System Resources, some of which have been previously listed, The quickest path to understanding the PSoC silicon is by provide additional capability useful to complete systems. reading this data sheet and using the PSoC Designer Integrated Additional resources include a multiplier, decimator, switch mode Development Environment (IDE). This data sheet is an overview pump, low voltage detection, and power on reset. Brief st
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Results CY8C24123 CY8C24223, CY8C24423 PSoC Designer Software Subsystems Development Tools ® Device Editor The Cypress MicroSystems PSoC Designer is a Microsoft Windows-based, integrated development environment for the The Device Editor subsystem allows the user to select different Programmable System-on-Chip (PSoC) devices. The PSoC onboard analog and digital components called user modules Designer IDE and application runs on Windows 98, Windows NT using the PSoC blocks. Examples of user module
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CY8C24123 CY8C24223, CY8C24423 Debugger User Modules and the PSoC Development The PSoC Designer Debugger subsystem provides hardware Process in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC The development process for the PSoC device differs from that device. Debugger commands allow the designer to read and of a traditional fixed function microprocessor. The configurable program and read and write data memory, read
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CY8C24123 CY8C24223, CY8C24423 Figure 5. User Module and Source Code Development Flows Document Conventions Acronyms Used Device Editor The following table lists the acronyms that are used in this Placement document. User Source and Module Code Table 2. Acronyms Parameter Selection Generator -ization Acronym Description AC alternating current ADC analog-to-digital converter Generate API application programming interface Application CPU central processing unit Application Editor CT continuo
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CY8C24123 CY8C24223, CY8C24423 Pinouts The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 8-Pin Part Pinout Table 3. 8-Pin Part Pinout (PDIP, SOIC) Type Figure 6. CY8C24123 8-Pin PSoC Device Pin Pin Description No. Name Digital Analog AIO, P0[5] Vdd 1 8 1 IO IO P0[5] Analog column mux input and co
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CY8C24123 CY8C24223, CY8C24423 28-Pin Part Pinout Table 5. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Type Figure 8. CY8C24423 28-Pin PSoC Device Pin Pin Description No. Name Digital Analog AI, P0[7] 1 IO I P0[7] Analog column mux input 1 28 Vdd AIO, P0[5] P0[6], AI 2 27 2 IO IO P0[5] Analog column mux input and column AIO, P0[3] P0[4], AI 3 26 output AI, P0[1] 4 25 P0[2], AI 3 IO IO P0[3] Analog column mux input and column P2[7] P0[0], AI 5 24 output P2[5] P2[6], External VRef 6 23 PDIP A
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CY8C24123 CY8C24223, CY8C24423 32-Pin Part Pinout Table 6. 32-Pin Part Pinout (MLF*) Type Figure 9. CY8C24423 32-Pin PSoC Device Pin Pin Description No. Name Digital Analog 1 IO P2[7] 2 IO P2[5] 3 IO I P2[3] Direct switched capacitor block input 4 IO I P2[1] Direct switched capacitor block input P2[7] 1 P0[2], AI 24 5 Power Vss Ground connection P2[5] 2 23 P0[0], AI AI, P2[3] 3 22 6 Power SMP Switch Mode Pump (SMP) P2[6], External VRef AI, P2[1] 4 21 P2[4], External AGND connection to extern
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CY8C24123 CY8C24223, CY8C24423 Register Mapping Tables Register Reference The PSoC device has a total register address space of 512 This section lists the registers of the CY8C27xxx PSoC device bytes. The register space is also referred to as IO space and is by way of mapping tables, in offset order. For detailed register broken into two parts. The XOI bit in the Flag register determines information, reference the PSoC Programmable which bank the user is currently in. When the XOI bit is set, th
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CY8C24123 CY8C24223, CY8C24423 Table 8. Register Map Bank 0 Table: User Space PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD
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CY8C24123 CY8C24223, CY8C24423 Table 8. Register Map Bank 0 Table: User Space (continued) DCB03DR2 2E RW 6E AE ACC_DR3 EE RW DCB03CR0 2F # 6F AF ACC_DR2 EF RW 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDIOLT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D
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CY8C24123 CY8C24223, CY8C24423 Table 9. Register Map Bank 1 Table: Configuration Space (continued) 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW 23 AMD_CR0 63 RW A3 VLT_CR E3 RW DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR
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Vdd Voltage Valid Operating e i n R g o CY8C24123 CY8C24223, CY8C24423 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x23 PSoC device. For latest electrical specifications, http://www.cypress.com. o o o Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C, except where noted. Specifications for devices running at greater than A J o o o 12 MHz are valid for -40 C ≤ T ≤ 70 C and T ≤ 82 C. A J Figure 10. Voltage versus Operating Frequenc
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CY8C24123 CY8C24223, CY8C24423 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 11. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes o T Storage Temperature -55 – +100 C Higher storage temperatures STG reduce data retention time. o T Ambient Temperature with Power Applied -40 – +85 C A Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V DC Input Voltage Vss - 0.5 – Vdd + 0.5 V IO – DC V
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CY8C24123 CY8C24223, CY8C24423 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. Table 13. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd Sup
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CY8C24123 CY8C24223, CY8C24423 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. Table 14. DC GPIO Specifications Symbol Description Min Typ Max Units Notes R Pull up Resistor 4 5.6 8 k Ω PU R P
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CY8C24123 CY8C24223, CY8C24423 Table 15. 5V DC Operational Amplifier Specifications (continued) Symbol Description Min Typ Max Units Notes G Open Loop Gain – – dB Specification is appli- OLOA Power = Low 60 cable at high power. For Power = Medium 60 all other bias modes Power = High 80 (except high power, high opamp bias), minimum is 60 dB. V High Output Voltage Swing (worst case internal load) OHIGHOA Power = Low Vdd - 0.2 – – V Power = Medium Vdd - 0.2 – – V Power = High Vdd - 0.5 – – V
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CY8C24123 CY8C24223, CY8C24423 Table 16. 3.3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input Offset Voltage (absolute value) Low Power – 1.65 10 mV OSOA Input Offset Voltage (absolute value) Mid Power – 1.32 8 mV High Power is 5 Volt Only o TCV Average Input Offset Voltage Drift – 7.0 35.0 μV/ C OSOA I Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA. EBOA C Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin
