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CY8C20x36/46/66, CY8C20396
CapSense™ Applications
Features
■ 1.71V to 5.5V Operating Range ■ Versatile Analog Mux
❐ Common Internal Analog Bus
■ Low Power CapSense™ Block
❐ Simultaneous Connection of IO
❐ Configurable Capacitive Sensing Elements
❐ High PSRR Comparator
❐ Supports Combination of CapSense Buttons, Sliders,
❐ Low Dropout Voltage Regulator for All Analog Resources
Touchpads, Touch Screens, and Proximity Sensor
■ Additional System Resources
■ Powerful Harvard Architecture Processor
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CY8C20x36/46/66, CY8C20396 Block Diagram 1.8/2.5/3V PWRSYS Port 4 Port 3 Port 2 Port 1 Port 0 LDO (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K 8K/16K/32K Flash Supervisory ROM (SROM) SRAM Nonvolatile Memory Interrupt Sleep and Controller CPU Core (M8C) Watchdog 6/12/24 MHz Internal Main Oscillator Internal Low Speed Oscillator (ILO) (IMO) Multiple Clock Sources CAPSENSE Analog Reference SYSTEM CapSense Module Two Analog Comparators Mux SYSTEM BUS I
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CY8C20x36/46/66, CY8C20396 ® Figure 1. Analog System Block Diagram PSoC Functional Overview The PSoC family consists of on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based components with one, low cost single-chip programmable IDAC component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each
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CY8C20x36/46/66, CY8C20396 Additional System Resources Getting Started System Resources, some of which are listed in the previous The quickest way to understand PSoC silicon is to read this data sections, provide additional capability useful to complete sheet and then use the PSoC Designer Integrated Development systems. Additional resources include low voltage detection and Environment (IDE). This data sheet is an overview of the PSoC power on reset. The merits of each system resource are liste
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CY8C20x36/46/66, CY8C20396 Development Tools ® PSoC Designer™ is a Microsoft Windows-based, integrated Code Generation Tools development environment for the Programmable System-on- PSoC Designer supports multiple third-party C compilers and Chip (PSoC) devices. The PSoC Designer IDE and application assemblers. The code generation tools work seamlessly within runs on Windows XP and Windows Vista. the PSoC Designer interface and have been tested with a full This system provides design database ma
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CY8C20x36/46/66, CY8C20396 Designing with PSoC Designer The development process for the PSoC device differs from that Organize and Connect of a traditional fixed function microprocessor. The configurable You build signal chains at the chip level by interconnecting user analog and digital hardware blocks give the PSoC architecture a modules to each other and the IO pins, or connect system-level unique flexibility that pays dividends in managing specification inputs, outputs, and communication int
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CY8C20x36/46/66, CY8C20396 Document Conventions Acronyms Used Units of Measure The following table lists the acronyms that are used in this A units of measure table is located in the Electrical Specifications document. section. Table 9 on page 15 lists all the abbreviations used to measure the PSoC devices. Table 1. Acronyms Numeric Naming Acronym Description Hexadecimal numbers are represented with all letters in AC alternating current uppercase with an appended lowercase ‘h’ (for example, ‘14
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CY8C20x36/46/66, CY8C20396 Pinouts The CY8C20x36/46/66, CY8C20396 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO. 16-Pin QFN [2] Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device Type Figure 2. CY8C20236, CY8C20246 PSoC Device Pin Name Description No. Digital
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CY8C20x36/46/66, CY8C20396 24-Pin QFN [2, 3] Table 3. Pin Definitions - CY8C20336, CY8C20346 Type Figure 3. CY8C20336, CY8C20346 PSoC Device Pin Name Description No. Digital Analog 1 IO I P2[5] Crystal output (XOut) 2 IO I P2[3] Crystal input (XIn) AI, XOut, P2[5] 1 18 P0[4], AI 3 IO I P2[1] AI, XIn, P2[3] 2 17 P0[2], AI 4 IOHR I P1[7] I2C SCL, SPI SS AI, P2[1] 3 QFN 16 P0[0], AI 15 5 IOHR I P1[5] I2C SDA, SPI MISO AI, I2C SCL, SPI SS, P1[7] 4 (Top View) P2[0], AI AI, I2C SDA, SPI MISO
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CY8C20x36/46/66, CY8C20396 24-Pin QFN with USB Pinout [2, 3] Table 4. Pin Definitions - CY8C20396 PSoC Device Type Pin No. Name Description Figure 4. CY8C20396 PSoC Device Digital Analog 1 IO I P2[5] 2 IO I P2[3] 3 IO I P2[1] 18 P2[5] 1 P0[2] 4 IOHR I P1[7] I2C SCL, SPI SS P2[3] 2 17 P0[0] P2[1] 3 QFN 16 XRES 5 IOHR I P1[5] I2C SDA, SPI MISO 15 I2C SCL, SPI SS, P1[7] 4 P1[6] (Top View) 6 IOHR I P1[3] SPI CLK I2C SDA, SPI MISO, P1[5] 5 14 P1[4], EXTCLK SPI CLK, P1[3] 6 13 P1[2] 7 IOHR I
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CY8C20x36/46/66, CY8C20396 32-Pin QFN [2, 3] Table 5. Pin Definitions - CY8C20436/46/66 PSoC Device Type Figure 5. CY8C20436/46/66 PSoC Device Pin Name Description No. Digital Analog 1 IOH I P0[1] Integrating input 2 IO I P2[7] 3 IO I P2[5] Crystal output (XOut) AI, P0[1] 1 24 P0[0], AI 4 IO I P2[3] Crystal input (XIn) AI, P2[7] 2 23 P2[6], AI 5 IO I P2[1] AI, XOut, P2[5] 3 22 P2[4], AI AI, XIn, P2[3] 4 21 P2[2], AI QFN 6 IO I P3[3] AI, P2[1] 5 20 P2[0], AI (Top View) 7 IO I P3[1] AI, P3[
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CY8C20x36/46/66, CY8C20396 48-Pin QFN [2, 3] Table 6. Pin Definitions - CY8C20666 PSoC Device Figure 6. CY8C20666 PSoC Device Pin Name Description No. 1 NC No connection NC 36 P2[6], AI 2 IO I P2[7] 1 AI, P2[7] 35 2 P2[4], AI 3 IO I P2[5] Crystal output (XOut) AI, XOut, P2[5] 34 P2[2], AI 3 4 IO I P2[3] Crystal input (XIn) 33 AI, XIn , P2[3] 4 P2[0], AI 5 IO I P2[1] AI , P2[1] 32 P4[2], AI 5 AI, P4[3] 6 QFN 31 P4[0], AI 6 IO I P4[3] AI, P4[1] 30 7 (Top View) P3[6], AI 7 IO IP4[1] P3[4],
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CY8C20x36/46/66, CY8C20396 48-Pin SSOP [2] Table 7. Pin Definitions - CY8C20566 PSoC Device Figure 7. CY8C20566 PSoC Device Name Description P0[7] 1 48 VDD P0[5] 2 47 P0[6] 1 IOH IO P0[7] P0[3] 3 P0[4] 46 2 IOH IO P0[5] P0[1] 4 45 P0[2] 3 IOH IO P0[3] P2[7] 5 P0[0] 44 P2[5] 6 4 IOH IO P0[1] 43 P2[6] P2[3] 7 P2[4] 42 5 IO IO P2[7] P2[1] 8 P2[2] 41 6 IO IO P2[5] XTAL Out NC 9 P2[0] 40 7 IO IO P2[3] XTAL In NC 10 39 P3[6] P4[3] 11 8 IO IO P2[1] 38 P3[4] P4[1] 12 37 P3[2] 9 NC No connection SSOP
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CY8C20x36/46/66, CY8C20396 48-Pin QFN OCD The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit [4] debugging. [2, 3] Table 8. Pin Definitions - CY8C20066 PSoC Device Figure 8. CY8C20066 PSoC Device Pin Name Description No. 1 OCDOE OCD mode direction pin OCDO 2 IO I P2[7] 36 P2[6], AI 1 E A 35 3 IO I P2[5] Crystal output (XOut) , P2[7] 2 P2[4], AI I AI, XOut, P2[5] 34 3 P2[2], AI 4 IO I P2[3] Crystal input (XIn) AI, XIn ,
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Valid O rating pe Region CY8C20x36/46/66, CY8C20396 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36/46/66, CY8C20396 PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options 5.5V 5.5V SLIMO SLIMO SLIMO Mode Mode Mode = 01 = 00 =
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CY8C20x36/46/66, CY8C20396 Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V. Table 10. Comparator User Module Electrical Specifications Symbol Description Min Typ Max Units Conditions T Comparator Response Time 70 100 ns 50 mV overdrive COMP Offset 2.5 30 mV Current 2
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CY8C20x36/46/66, CY8C20396 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units T Storage Temperature Higher storage temperatures reduces data –55 +25 +125 °C STG retention time. Recommended Storage Temperature is +25°C ± 25°C. Extended o duration storage temperatures above 85 C degrades reliability. Vdd Supply Voltage Relative to Vss –
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CY8C20x36/46/66, CY8C20396 DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and –40°C ≤ T ≤ 85°C, 2.4V to 3.0V and –40°C ≤ T ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ T ≤ 85°C, respectively. Typical parameters A A A apply to 5V and 3.3V at 25°C and are for design guidance only. Table 15. 3.0V to 5.5V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units R Pull up Resist
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CY8C20x36/46/66, CY8C20396 Table 16. 2.4V to 3.0V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units R Pull up Resistor 4 5.6 8 k Ω PU V High Output Voltage IOH < 10 μA, maximum of 10 mA Vdd - 0.2 – – V OH1 Port 2 or 3 Pins source current in all IOs V High Output Voltage IOH = 0.2 mA, maximum of 10 mA Vdd - 0.4 – – V OH2 Port 2 or 3 Pins source current in all IOs V High Output Voltage IOH < 10 μA, maximum of 10 mA Vdd - 0.2 – – V OH3 Port 0 or 1 Pins with LDO Regulator s
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CY8C20x36/46/66, CY8C20396 Table 17. 1.71V to 2.4V DC GPIO Specifications (continued) Symbol Description Conditions Min Typ Max Units V Input Hysteresis Voltage – 80 – mV H I Input Leakage (Absolute Value) – 0.001 1 μA IL C Capacitive Load on Pins Package and pin dependent 0.5 1.7 5 pF PIN o Temp = 25 C Table 18.DC Characteristics – USB Interface Symbol Description Conditions Min Typ Max Units Rusbi USB D+ Pull Up Resistance With idle bus 0.900 - 1.575 k Ω Rusba USB D+ Pull Up Resistance While
