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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
[1]
Features Functional Description
• Supports 133 MHz bus operations The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
• 512K x 36/1M x 18 common IO
synchronous flow through SRAMs, designed to interface with
• 2.5V core power supply (V )
DD
high-speed microprocessors with minimum glue logic.
• 2.5V IO supply (V )
Maximum access delay from clock rise is 6.5
Resumo do conteúdo contido na página número 2
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 [3] Logic Block Diagram – CY7C1381DV25/CY7C1381FV25 (512K x 36) ADDRESS A0, A1, A REGISTER A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTE BYTE WRITE REGISTER WRITE REGISTER WRITE REGISTER DQ C , DQP C DQ C , DQP C BW C WRITE REGISTER OUTPUT DQs WRITE REGISTER MEMORY SENSE BUFFERS DQP A ARRAY DQ B, DQP B AMPS DQ B, DQP B DQP B BW B DQP C WRITE REGISTER WRITE REGISTER DQP D DQ A, DQP DQ A
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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations 100-pin TQFP Pinout (3 Chip Enable) DQP C 1 80 DQP B NC A 1 80 DQ C 2 79 DQ B NC NC 2 79 DQ C 3 78 DQ B NC NC 3 78 V DDQ 4 77 V DDQ V V DDQ 4 77 DDQ V SSQ V 5 76 V SSQ SSQ 5 76 V SSQ DQ C DQ 6 75 NC B 6 75 NC DQ C DQ 7 74 NC B 7 74 DQP A DQ C DQ 8 73 DQ B B 8 73 DQ A DQ DQ C 9 72 DQ B B 9 72 DQ A V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQ C 12 69 DQ B DQ B DQ 12 69 A DQ C 13 68 DQ B DQ B DQ 1
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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations (continued) 119-Ball BGA Pinout CY7C1381FV25 (512K x 36) 1 23 4 5 6 7 A V AA A A V DDQ ADSP DDQ B NC/288M AA A A NC/576M ADSC C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B DQ DQ V V DQ DQ E CE C C SS SS B B 1 F V DQ V V DQ V OE DDQ C SS SS B DDQ G DQ DQ DQ DQ BW ADV BW C C B B C B H DQ DQ V V DQ DQ C C SS GW SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ NC DQ DQ BW
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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381DV25 (512K x 36) 1 23 4 5 6 7 89 10 11 A NC/288M CE BW BW CE BWE ADSC ADV A NC A 1 C B 3 B NC/144M A CE BW BW CLK GW OE ADSP A NC/576M 2 D A DQP NC V V V V V V V NC/1G DQP C C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C C DDQ DD SS SS SS DD
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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Definitions Name IO Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the rising edge 0 1 [2] Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. 1 2 3 A feed the 2-bit counter. [1:0] BW , BW Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the A B BW , BW Synchronous SRAM. Sampled on the rising edge o
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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Definitions (continued) Name IO Description MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V or DD left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. V Power Supply Power supply inputs to the core of the device. DD V IO Power Supply Power supply for the IO circuitry. DDQ V Ground Gro
Resumo do conteúdo contido na página número 8
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 and the IOs must be tri-stated prior to the presentation of data Sleep Mode to DQs. As a safety precaution, the data lines are tri-stated The ZZ input pin is an asynchronous input. Asserting ZZ once a write cycle is detected, regardless of the state of OE. places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep Single Write Accesses Initiated by ADSC mode. While in this mode, dat
Resumo do conteúdo contido na página número 9
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 [4, 5, 6, 7, 8] Truth Table Address Cycle Description CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Used Deselected Cycle, Power None H X X L X L X X X L-H Tri-State Down Deselected Cycle, Power None L L X L L X X X X L-H Tri-State Down Deselected Cycle, Power None L X H L L X X X X L-H Tri-State Down Deselected Cycle, Power None L L X L H L X X X L-H Tri-State Down Deselected Cycle, Power None X X X L H L X X X L-H Tri-State Down Sleep M
Resumo do conteúdo contido na página número 10
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 [4, 9] Truth Table for Read/Write Function (CY7C1381DV25/CY7C1381FV25) GW BWE BW BW BW BW D C B A Read H H X X X X Read H L H H H H Write Byte A (DQ , DQP)HLHHHL A A Write Byte B (DQ , DQP)HLHHLH B B Write Bytes A, B (DQ , DQ , DQP , DQP)H L H H L L A B A B Write Byte C (DQ , DQP) H LHLH H C C Write Bytes C, A (DQ , DQ DQP , DQP) H LHLH L C A, C A Write Bytes C, B (DQ , DQ DQP , DQP)H L H L L H C B, C B Write Bytes C, B, A (DQ , DQ , DQ DQP
Resumo do conteúdo contido na página número 11
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the The CY7C1381DV25/CY7C1383DV25 incorporates a serial registers and can be connected to the input of any of the boundary scan test access port (TAP). This part is fully registers. The register between TDI and TDO is chosen by the compliant with 1149.1. The TAP operates using instruction that is loaded into the TAP instruction r
Resumo do conteúdo contido na página número 12
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 When the TAP controller is in the Capture-IR state, the two the IDCODE to be shifted out of the device when the TAP least significant bits are loaded with a binary ‘01’ pattern to controller enters the Shift-DR state. allow for fault isolation of the board level serial test data path. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test Bypass Register logic reset state. T
Resumo do conteúdo contido na página número 13
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 the TAP controller, it will directly control the state of the output register. When the EXTEST instruction is entered, this bit will (Q-bus) pins, when the EXTEST is entered as the current directly control the output Q-bus pins. Note that this bit is instruction. When HIGH, it will enable the output buffers to preset HIGH to enable the output when the device is powered drive the output bus. When LOW, this bit will place the output up, and als
Resumo do conteúdo contido na página número 14
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent 1.25V Input pulse levels .................................................V to 2.5V SS Input rise and fall time..................................................... 1 ns 50Ω Input timing reference levels.........................................1.25V Output reference levels.................................................1.25V TDO Test load termination supply voltage...............
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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM
Resumo do conteúdo contido na página número 16
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 [13, 15] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N7 32 C11 62 D2 3 N10 33 A11 63 E2 4P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3
Resumo do conteúdo contido na página número 17
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage.......................................... > 2001V the device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C La
Resumo do conteúdo contido na página número 18
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 [18] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package C Input Capacitance T = 25°C, f = 1 MHz, 58 9 pF IN A V /V = 2.5V DD DDQ C Clock Input Capacitance 5 8 9 pF CLK C Input/Output Capacitance 5 8 9 pF IO [18] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package Θ Thermal Resistance Test conditions follow 28.66 23.8 20.7 °C/W
Resumo do conteúdo contido na página número 19
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Switching Characteristics [19, 20] Over the Operating Range 133 MHz 100 MHz Parameter Description Unit Min. Max. Min. Max. [21] t V (Typical) to the first Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 2.1 2.5 ns CH t Clock LOW 2.1 2.5 ns CL Output Times t Data Output Valid After CLK Rise 6.5 8.5 ns CDV t Data Output Hold After CLK Rise 2.0 2.0 ns DOH [22, 23, 24] t Clock to Low-Z 2.0 2.0 ns CLZ [22, 23, 24] t Clock
Resumo do conteúdo contido na página número 20
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams [25] Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH A1 A2 ADDRESS t t WES WEH GW, BWE,BW X Deselect Cycle t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Data Out (Q) High-Z Q(A1) t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 25. On
