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CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
Features Functional Description
• Separate independent Read and Write data ports
The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM
— Supports concurrent transactions equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
• 167-MHz clock for high bandwidth
port has dedicated data outputs to support Read operations
— 2.5 ns Clock-to-Valid access time
and the Wr
Resumo do conteúdo contido na página número 2
CY7C1302DV25 Selection Guide CY7C1302DV25-167 Unit Maximum Operating Frequency 167 MHz Maximum Operating Current 500 mA Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1302DV25 (512K x 18) 1 2 345 6789 10 11 A NC Gnd/144M NC/36M WPS BWS K NC RPS NC/18M Gnd/72M NC 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD
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CY7C1302DV25 Pin Definitions (continued) Name I/O Description C Input- Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data Clock from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
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CY7C1302DV25 Synchronous internal circuitry will automatically three-state registers. This operation is identical to the operation if the the outputs following the next rising edge of the positive output device had zero skew between the K/K and C/C clocks. All clock (C). This will allow for a seamless transition between timing parameters remain the same in this mode. To use this devices without the insertion of wait states in a depth mode of operation, the user must tie C and C HIGH at expanded
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CY7C1302DV25 [2, 3, 4, 5, 6, 7] Truth Table Operation K RPS WPS DQ DQ Write Cycle: L-H X L D(A+0) at K(t) ↑ D(A+1) at K(t) ↑ Load address on the rising edge of K clock; input write data on K and K rising edges. Read Cycle: L-H L X Q(A+0) at C(t+1)↑ Q(A+1) at C(t+1) ↑ Load address on the rising edge of K clock; wait one cycle; read data on 2 consecutive C and C rising edges. NOP: No Operation L-H H H D = X D = X Q = High-Z Q = High-Z Standby: Clock Stopped Stopped X X Previous State Previou
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CY7C1302DV25 TDI and TDO pins as shown in TAP Controller Block Diagram. IEEE 1149.1 Serial Boundary Scan (JTAG) Upon power-up, the instruction register is loaded with the These SRAMs incorporate a serial boundary scan test access IDCODE instruction. It is also loaded with the IDCODE port (TAP) in the FBGA package. This part is fully compliant instruction if the controller is placed in a reset state as with IEEE Standard #1149.1-1900. The TAP operates using described in the previous section. JEDE
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CY7C1302DV25 is loaded into the instruction register upon power-up or BYPASS whenever the TAP controller is given a test logic reset state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass SAMPLE Z register is placed between the TDI and TDO pins. The The SAMPLE Z instruction causes the boundary scan register advantage of the BYPASS instruction is that it shortens the to be connected between the TDI and TDO pins when the TAP b
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CY7C1302DV25 [9] TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05625 Rev. *A Page 8 of 18 [+] Feedback
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CY7C1302DV25 TAP Controller Block Diagram 0 Bypass Register Selection Selection TDI 2 1 0 TDO Circuitry Circuitry Instruction Register 29 31 30 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS [10, 13, 15] TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = −2.0 mA 1.7 V OH1 OH V Output HIGH Voltage I = −100 µA2.1 V OH2 OH V Output LOW Voltage I = 2.0 mA 0.7 V
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CY7C1302DV25 [11, 12] TAP AC Switching Characteristics Over the Operating Range (continued) Parameter Description Min. Max. Unit Output Times t TCK Clock LOW to TDO Valid 20 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX [12] TAP Timing and Test Conditions 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z = 50Ω 0 1.25V = 20 pF C L 0V (a) GND t TL t TH Test Clock TCK t TCYC t TMSS t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t t TDOX TDOV Identification Register Definitions
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CY7C1302DV25 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z
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CY7C1302DV25 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43 11C 70 3C 9
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CY7C1302DV25 Static Discharge Voltage........................................... >2001V Maximum Ratings (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired.) Latch-up Current..................................................... >200 mA Storage Temperature .................................–65°C to + 150°C Operating Range Ambient Temperature with Power Applied............................................–55°C to + 125°C Ambient [14] [14] Range Temperature (T)V V A DD DDQ Sup
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CY7C1302DV25 [20] Thermal Resistance Parameter Description Test Conditions 165 FBGA Package Unit Θ Thermal Resistance (Junction to Ambient) Test conditions follow standard test 16.7 °C/W JA methods and procedures for measuring Θ Thermal Resistance (Junction to Case) 2.5 °C/W JC thermal impedance, per EIA/JESD51. [20] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 2.5V. DD C Clock Input Capacitance 6 pF CLK V = 1.5V DDQ C Ou
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CY7C1302DV25 [21] Switching Characteristics Over the Operating Range (continued) 167 MHz Cypress Consortium Parameter Parameter Description Min. Max. Unit Output Times t t C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns CO CHQV t t Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns DOH CHQX [23, 24] t t Clock (C and C) Rise to High-Z (Active to High-Z) 2.5 ns CHZ CHZ [23, 24] t t Clock (C and C) Rise to Low-Z 1.2 ns CLZ CLZ Notes: 23. t , t , are specified
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CY7C1302DV25 [25, 26, 27] Switching Waveforms READ WRITE READ WRITE READ WRITE NOP WRITE NOP 12345 6 7 8 9 10 K t t t t KH KL CYC KHKH K RPS tSC tHC WPS A5 A6 A0 A1 A2 A3 A4 A t t t t SA HA SA HA D D10 D11 D30 D31 D50 D51 D60 D61 t t t SD HD HD t SD Q Q00 Q01 Q20 Q21 Q40 Q41 t CHZ t t t DOH DOH CLZ t t t t KHCH KHCH CO CO C t t t tCYC KH KL KHKH C DON’T CARE UNDEFINED Notes: 25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0
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CY7C1302DV25 Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 167 CY7C1302DV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1302DV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free CY7C1302DV25-167BZI 165-ball Fine Pi
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CY7C1302DV25 Document History Page Document Title:CY7C1302DV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture Document Number: 38-05625 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 253010 See ECN SYT New Data Sheet *A 436864 See ECN NXR Converted from Preliminary to Final Removed 133 MHz & 100 MHz from product offering Included the Industrial Operating Range. Changed C/C Description in the Features Section & Pin Description Table Changed t from 100 ns to 50 ns, chang
