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PRELIMINARY
CY14B108L, CY14B108N
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times The Cypress CY14B108L/CY14B108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 1024K x 8 (CY14B108L) or 512K x 16
organized as 1024 Kbytes of 8 bits each or 512K words of 16 bits
(CY14B108N)
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most re
Resumo do conteúdo contido na página número 2
PRELIMINARY CY14B108L, CY14B108N Pinouts Figure 1. Pin Diagram - 48 FBGA 48-FBGA 48-FBGA (x8) (x16) Top View Top View (not to scale) (not to scale) 1 2 4 5 3 6 1 4 2 3 5 6 A A A OE NC A A A BLE 0 2 A OE NC 1 NC 0 1 2 A DQ A A NC 8 BHE CE DQ B A A 3 4 NC CE NC B 0 3 4 C DQ A A DQ DQ A A C DQ DQ NC NC DQ 9 5 6 1 2 5 10 0 6 4 V A V A A DQ V A V SS DQ 7 CC D SS DQ 7 DQ CC D 17 3 17 5 11 1 V A V E V A V CC DQ V DQ SS DQ V DQ SS E CAP 16 CC 16 12 4 2 CAP 6 A A F A A F DQ DQ DQ DQ NC DQ 13 14 DQ NC
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PRELIMINARY CY14B108L, CY14B108N Table 1. Pin Definitions Pin Name I/O Type Description A – A Input Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration. 0 19 A – A Address Inputs Used to Select one of the 524,288 words of the nvSRAM for x16 Configuration. 0 18 DQ – DQ Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on 0 7 operation. DQ – DQ Bidirectional Data IO Lines for x16 Configuration. Used as i
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PRELIMINARY CY14B108L, CY14B108N Figure 3 shows the proper connection of the storage capacitor Device Operation (V ) for automatic STORE operation. Refer to DC Electrical CAP The CY14B108L/CY14B108N nvSRAM is made up of two Characteristics on page 8 for the size of V . The voltage on CAP functional components paired in the same physical cell. They are the V pin is driven to V by a regulator on the chip. A pull CAP CC a SRAM memory cell and a nonvolatile QuantumTrap cell. The up should be placed
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PRELIMINARY CY14B108L, CY14B108N STORE operation is completed, the CY14B108L/CY14B108N The software sequence may be clocked with CE controlled reads remains disabled until the HSB pin returns HIGH. Leave the HSB or OE controlled reads. After the sixth address in the sequence unconnected if it is not used. is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. It is important to use read cycles Hardware RECALL (Power Up) and not write cycles in the sequence, although i
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PRELIMINARY CY14B108L, CY14B108N Table 2. Mode Selection [5] [3] A - A Mode IO Power CE WE OE, BHE, BLE 15 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active [6] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable [6] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Dat
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PRELIMINARY CY14B108L, CY14B108N Preventing AutoStore Noise Considerations The AutoStore function is disabled by initiating an AutoStore Refer to CY application note AN1064. disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate Best Practices the AutoStore disable sequence, the following sequence of CE nvSRAM products have been used effectively for over 15 years. controlled read operations must be performed: While ease-of-u
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PRELIMINARY CY14B108L, CY14B108N Transient Voltage (<20 ns) on Maximum Ratings Any Pin to Ground Potential................ ..–2.0V to V + 2.0V CC Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device. These user guidelines are not tested. Capability (T = 25°C)....................................................1.0W A Storage Temperature ..................................–65 °C to +150 °C Surface Mount Pb Soldering Temperature (3 Seconds)..................
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PRELIMINARY CY14B108L, CY14B108N Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [10] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 14 pF IN A V = 0 to 3.0V CC C Output Capacitance 14 pF OUT Thermal Resistance [10] In the following table, the thermal resistance parameters are listed. Parameter Des
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PRELIMINARY CY14B108L, CY14B108N AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [11] t t Read Cycle Time 20 25 45 ns RC RC [12] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE [12] t t Output Hold After Address Change 3 3 3 ns OHA OH [10, 13] t t Chip Enable to Output Active 3 3 3 ns LZCE LZ [10, 13] t
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PRELIMINARY CY14B108L, CY14B108N [3, 11, 15] Figure 6. SRAM Read Cycle #2: CE and OE Controlled Address Address Valid t t HZCE RC t ACE CE t AA t t LZCE HZOE t DOE OE t t HZBE LZOE t DBE BHE, BLE t LZBE High Impedance Data Output Output Data Valid t PU t PD Active I Standby CC [3, 14, 15, 16] Figure 7. SRAM Write Cycle #1: WE Controlled Notes 16. CE or WE must be >V during address transitions. IH Document #: 001-45523 Rev. *B Page 11 of 24 [+] Feedback
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PRELIMINARY CY14B108L, CY14B108N [3, 14, 15, 16] Figure 8. SRAM Write Cycle #2: CE Controlled t WC Address Valid Address t t t SA SCE HA CE t BW BHE, BLE t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Output [3, 14, 15, 16] Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled t WC Address Address Valid t SCE CE t t t SA HA BW BHE, BLE t AW t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Output Document #: 001-45523 Rev. *B Page 12 of 24 [+] Feedback
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PRELIMINARY CY14B108L, CY14B108N AutoStore/Power Up RECALL 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max [17] t Power Up RECALL Duration 20 20 20 ms HRECALL [18] t STORE Cycle Duration 8 8 8 ms STORE [19] t Time Allowed to Complete SRAM Cycle 20 25 25 ns DELAY V Low Voltage Trigger Level 2.65 2.65 2.65 V SWITCH t VCC Rise Time 150 150 150 μs VCCRISE [10] V HSB Output Driver Disable Voltage 1.9 1.9 1.9 V HDIS t HSB To Output Active Time 5 5 5 μs LZHSB t HSB High Active
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PRELIMINARY CY14B108L, CY14B108N Software Controlled STORE/RECALL Cycle [22, 23] In the following table, the software controlled STORE and RECALL cycle parameters are listed. 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t STORE/RECALL Initiation Cycle Time 20 25 45 ns RC t Address Setup Time 0 0 0 ns SA t Clock Pulse Width 15 20 30 ns CW t Address Hold Time 0 0 0 ns HA t RECALL Duration 200 200 200 μs RECALL Switching Waveforms [23] Figure 11. CE and OE Controlled Soft
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PRELIMINARY CY14B108L, CY14B108N Hardware STORE Cycle 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t HSB To Output Active Time when write latch not set 20 25 25 ns DHSB t Hardware STORE Pulse Width 15 15 15 ns PHSB [24, 25] t Soft Sequence Processing Time 100 100 100 μs SS Switching Waveforms [18] Figure 13. Hardware STORE Cycle Write latch set t PHSB HSB (IN) t STORE t t HHHD DELAY HSB (OUT) t LZHSB DQ (Data Out) RWI Write latch not set t PHSB HSB pin is driven high
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PRELIMINARY CY14B108L, CY14B108N Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration [2] CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ –DQ ); Read Active 0 7 L H H High Z Output Disabled Active L L X Data in (DQ –DQ ); Write Active 0 7 For x16 Configuration [3] [3] [2] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby L X X H H High-Z Output Disabled Active L
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PRELIMINARY CY14B108L, CY14B108N Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 20 CY14B108L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS20XC 51-85087 44-pin TSOP II CY14B108L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B108L-ZS20XI 51-85087 44-pin TSOP II CY14B108L-BA20XCT 51-85128 48-ball FBGA Commercial CY14B108L-BA20XC 51-85128 48-ball FBGA CY14B108L-BA20XIT 51-85128 48-ball FBGA Industrial CY14B108L-BA20XI 51-85128 48-ball FBGA CY14B
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PRELIMINARY CY14B108L, CY14B108N Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY14B108L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS45XC 51-85087 44-pin TSOP II CY14B108L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B108L-ZS45XI 51-85087 44-pin TSOP II CY14B108L-BA45XCT 51-85128 48-ball FBGA Commercial CY14B108L-BA45XC 51-85128 48-ball FBGA CY14B108L-BA45XIT 51-85128 48-ball FBGA Industrial CY14B108L-BA45XI 51-85128 48-bal
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PRELIMINARY CY14B108L, CY14B108N Part Numbering Nomenclature CY 14 B 108L-ZS P 20 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) Speed: I - Industrial (–40 to 85°C) Pb-Free 20 - 20 ns 25 - 25 ns P - 54 Pin Package: 45 - 45 ns Blank - 44 Pin/48 Ball BA - 48 FBGA ZS - TSOP II Data Bus: L - x8 N - x16 Density: 108 - 8 Mb Voltage: B - 3.0V NVSRAM 14 - Auto Store + Software STORE + Hardware STORE Cypress Document #: 001-45523 Rev. *B Page 19 of 24 [+] Feedback
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PRELIMINARY CY14B108L, CY14B108N Package Diagrams Figure 15. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document #: 001-45523 Rev. *B Page 20 of 24 [+] Feedback 1.194 (0.047) 0.991 (0.039)
