Resumo do conteúdo contido na página número 1
®
CY62167EV30 MoBL
16-Mbit (1M x 16 / 2M x 8) Static RAM
low active current. Ultra low active current is ideal for providing
Features
®
More Battery Life™ (MoBL ) in portable applications such as
cellular telephones. The device also has an automatic power
■ TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM
down feature that reduces power consumption by 99 percent
■ Very High Speed: 45 ns
when addresses are not toggling. Place the device into standby
mode when deselected (CE HIGH or CE LOW or
Resumo do conteúdo contido na página número 2
® CY62167EV30 MoBL Pin Configuration [1, 2, 3] Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View 1 2 3 4 5 6 A A A CE BLE OE 0 1 2 2 A A A I/O BHE CE I/O B 3 8 4 1 0 A A C I/O I/O I/O I/O 9 10 5 6 1 2 V A V I/O A I/O CC SS 7 D 11 17 3 Vss NC A V I/O E CC I/O 12 16 4 F I/O I/O A A I/O I/O 13 14 15 14 5 6 A I/O A G A WE I/O 12 13 15 19 7 A A A A A NC 9 10 11 H 18 8 [3, 4] Figure 2. 48-Pin TSOP I Top View A15 1 48 A16 A14 2 47 BYTE A13 3 46 Vss A12 4 45 IO15/A20 A11 5 44 IO7 A10 6
Resumo do conteúdo contido na página número 3
® CY62167EV30 MoBL [6, 7] DC Input Voltage ...........–0.3V to 3.9V (V (max) + 0.3V Maximum Ratings CC Output Current into Outputs (LOW) ............................ 20 mA Exceeding the maximum ratings may impair the useful life of the Static Discharge Voltage........................................... >2001V device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................ –65°C to + 150°C Latch up Current.............................
Resumo do conteúdo contido na página número 4
® CY62167EV30 MoBL Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. VFBGA VFBGA Parameter Description Test Conditions TSOP I Unit (6 x 7 x 1mm) (6 x 8 x 1mm) Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 27.74 55 60 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 9.84 16 4.3 °C/W JC (Junction to Case) Shaded areas contain preliminary information. Figure 3. AC Test Loads and Waveforms R1
Resumo do conteúdo contido na página número 5
® CY62167EV30 MoBL Switching Characteristics [14, 15] Over the Operating Range 45 ns (Industrial/Auto-A) Parameter Description Unit Min Max READ CYCLE t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 ns ACE 1 2 t OE LOW to Data Valid 22 ns DOE [16] t OE LOW to LOW Z 5ns LZOE [16, 17] t OE HIGH to High Z 18 ns HZOE [16] t CE LOW and CE HIGH to Low Z 10 ns LZCE 1 2 [16, 17] t CE HIGH and CE LOW to High Z
Resumo do conteúdo contido na página número 6
® CY62167EV30 MoBL Switching Waveforms [19, 20] Figure 5 shows address transition controlled read cycle waveforms. Figure 5. Read Cycle No. 1 t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [20, 21] Figure 6 shows OE controlled read cycle waveforms. Figure 6. Read Cycle No. 2 ADDRESS t RC CE 1 t PD t HZCE CE 2 t ACE BHE/BLE t DBE t HZBE t LZBE OE t HZOE t DOE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t I PU CC V CC 50% 50% SUPPLY I SB CURRENT Notes 19.
Resumo do conteúdo contido na página número 7
® CY62167EV30 MoBL Switching Waveforms (continued) [18, 22, 23] Figure 7 shows WE controlled write cycle waveforms. Figure 7. Write Cycle No. 1 t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 24 DATA I/O VALID DATA t HZOE Notes 22. Data IO is high impedance if OE = V . IH 23. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state. 1 2 IH 24. During this period the I/Os are in output state. Do not apply input
Resumo do conteúdo contido na página número 8
® CY62167EV30 MoBL Switching Waveforms (continued) [18, 22, 23] Figure 8 shows CE or CE controlled write cycle waveforms. 1 2 Figure 8. Write Cycle No. 2 t WC ADDRESS t SCE CE 1 CE 2 t SA t t AW HA t PWE WE t BW BHE/BLE OE t HD t SD DATA I/O NOTE 24 VALID DATA t HZOE [23] Figure 9 shows WE controlled, OE LOW write cycle waveforms. Figure 9. Write Cycle No. 3 t WC ADDRESS t SCE CE 1 CE 2 t BW BHE/BLE t t AW HA t t SA PWE WE t t SD HD NOTE 24 DATA I/O VALID DATA t t LZWE HZWE Document #: 38-0544
Resumo do conteúdo contido na página número 9
® CY62167EV30 MoBL Switching Waveforms (continued) [23] Figure 10 shows BHE/BLE controlled, OE LOW write cycle waveforms. Figure 10. Write Cycle No. 4 t WC ADDRESS CE 1 CE 2 t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t t SD HD DATA IO NOTE 24 VALID DATA Truth Table CE CE WE OE BHE BLE Inputs/Outputs Mode Power 1 2 H XXXXX High Z Deselect / Power Down Standby (I ) SB X L XXXX High Z Deselect / Power Down Standby (I ) SB XXXX H H High Z Deselect / Power Down Standby (I ) SB L H H L L L Data Out (
Resumo do conteúdo contido na página número 10
® CY62167EV30 MoBL Ordering Information Speed Package Operating Package Type (ns) Ordering Code Diagram Range 45 CY62167EV30LL-45BAXI 001-13297 48-ball VFBGA (6 x 7 x 1 mm) (Pb-free) Industrial CY62167EV30LL-45BVI 51-85150 48-ball VFBGA (6 x 8 x 1 mm) CY62167EV30LL-45BVXI 51-85150 48-ball VFBGA (6 x 8 x 1 mm) (Pb-free) CY62167EV30LL-45ZXI 51-85183 48-pin TSOP I (Pb-free) CY62167EV30LL-45ZXA 51-85183 48-pin TSOP I (Pb-free) Automotive-A Shaded areas contain preliminary information. Please contact
Resumo do conteúdo contido na página número 11
® CY62167EV30 MoBL Package Diagrams (continued) Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A B 0.75 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85150-*D Document #: 38-05446 Rev. *E Page 11 of 14 [+] Feedback 0.25 C 8.00±0.10 0.26 MAX. 0.55 MAX. 0.21±0.05 1.00 MAX 0.10 C 8.00±0.10 5.25 0.75 2.625
Resumo do conteúdo contido na página número 12
® CY62167EV30 MoBL Package Diagrams (continued) Figure 13. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] 1 N 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] 0.004[0.10] 0.010[0.25] 0.008[0.21] GAUGE PLANE 0.020[0.50] 0°-5° 0.028[0.70] 51-85183-*A Document #: 38-05446 Rev. *E Page 12 of 14 [+] Feedback SEATING PLANE 0.004[0.10]
Resumo do conteúdo contido na página número 13
® CY62167EV30 MoBL Document History Page ® Document Title: CY62167EV30 MoBL 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 38-05446 Orig. of Submission REV. ECN NO. Change Date Description of Change ** 202600 AJU 01/23/2004 New Data Sheet *A 463674 NXR See ECN Converted from Advance Information to Preliminary Removed ‘L’ bin and 35 ns speed bin from product offering Modified Data sheet to include x8 configurability. Changed ball E3 in FBGA pinout from DNU to NC Changed the I value from
Resumo do conteúdo contido na página número 14
® CY62167EV30 MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com General psoc.cypress.com/solutions Clocks & Buffers clocks.cypress.com Low Power/Low Voltage psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog psoc.cypr
