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®
CY62167DV18 MoBL
16-Mbit (1M x 16) Static RAM
consumption by more than 99% when deselected (CE HIGH
Features
1
or CE LOW or both BHE and BLE are HIGH). The input and
2
• Very high speed: 55 ns output pins (IO through IO ) are placed in a high impedance
0 15
state when:
• Wide voltage range: 1.65V–1.95V
• Deselected (CE HIGH or CE LOW)
1 2
• Ultra low active power
• Outputs are disabled (OE HIGH)
— Typical active current: 1.5 mA @ f = 1 MHz
• Both Byte High Enable (BHE) and Byte Low Enable (
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® CY62167DV18 MoBL Product Portfolio Power Dissipation V Range (V) Operating I (mA) CC CC Speed Product Standby I (µA) SB2 (ns) f = 1MHz f = f max [2] [2] [2] [2] Min Typ Max Typ Max Typ Max Typ Max CY62167DV18LL 1.65 1.8 1.95 55 1.5 5 15 30 2.5 20 [3] Pin Configuration 48-Ball VFBGA Top View 126 3 4 5 A A A CE A BLE OE 2 0 1 2 A A B IO BHE CE IO 3 4 8 1 0 A A C IO IO IO IO 5 6 9 10 1 2 V IO V A A IO D SS 11 CC 17 7 3 V A IO V IO DNU E CC 16 4 SS 12 IO A A IO IO IO F 13 14 15 5 6 14 A A I
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® CY62167DV18 MoBL [4, 5] DC Input Voltage ........................–0.2V to V + 0.2V Maximum Ratings CCmax Output Current into Outputs (LOW)............................. 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage.......................................... > 2001V the device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch up Current.........................
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® CY62167DV18 MoBL [7] Thermal Resistance Parameter Description Test Conditions VFBGA Unit Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 55 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 16 °C/W JC (Junction to Case) AC Test Loads and Waveforms R1 ALL INPUT PULSES V CC V CC OUTPUT 90% 90% 10% 10% GND R2 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THE VENIN EQUIVALENT R TH OUTPUT V Parameters 1.8V Unit R1
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® CY62167DV18 MoBL [10] Switching Characteristics (Over the Operating Range) 55 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 55 ns RC t Address to Data Valid 55 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 55 ns ACE 1 2 t OE LOW to Data Valid 25 ns DOE [11] t OE LOW to LOW Z 5ns LZOE [11, 12] t OE HIGH to High Z 20 ns HZOE [11] t CE LOW and CE HIGH to Low Z 10 ns LZCE 1 2 [11, 12] t CE HIGH and CE LOW to High Z 20 ns HZCE 1 2 t CE
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® CY62167DV18 MoBL Switching Waveforms [14, 15] Read Cycle 1 (Address Transition Controlled) t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 16] Read Cycle 2 (OE Controlled) ADDRESS t RC CE 1 t PD t HZCE CE 2 t ACE BHE/BLE t DBE t HZBE t LZBE OE t HZOE t DOE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE I t CC PU V CC 50% 50% SUPPLY I SB CURRENT Notes 14. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V . 1 IL IL 2 IH
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® CY62167DV18 MoBL Switching Waveforms (continued) [13, 17, 18] Write Cycle 1 (WE Controlled) t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD DATA IO NOTE 19 VALID DATA t HZOE [13, 17, 18] Write Cycle 2 (CE or CE Controlled) 1 2 t WC ADDRESS t SCE CE 1 CE 2 t SA t t AW HA t PWE WE t BW BHE/BLE OE t HD t SD DATA IO NOTE 19 VALID DATA t HZOE Notes 17. Data IO is high impedance if OE = V . IH 18. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the outp
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® CY62167DV18 MoBL Switching Waveforms (continued) [18] Write Cycle 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE 1 CE 2 t BW BHE/BLE t t AW HA t t SA PWE WE t t SD HD DATA IO NOTE 19 VALID DATA t LZWE t HZWE [18] Write Cycle 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE 1 CE 2 t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t t SD HD DATA IO NOTE 19 VALID DATA Document #: 38-05326 Rev. *C Page 8 of 11 [+] Feedback
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® CY62167DV18 MoBL Truth Table CE CE WE OE BHE BLE Inputs/Outputs Mode Power 1 2 H X X X X X High Z Deselect/Power Down Standby (I ) SB X L X X X X High Z Deselect/Power Down Standby (I ) SB X X X X H H High Z Deselect/Power Down Standby (I ) SB L H H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC L H H L H L High Z (IO –IO ); Read Active (I ) 8 15 CC Data Out (IO –IO ) 0 7 L H H L L H Data Out (IO –IO ); Read Active (I ) 8 15 CC High Z (IO –IO ) 0 7 LH LX L L Data In (IO –IO ) Write Activ
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® CY62167DV18 MoBL Package Diagrams Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05MC Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 8.00±0.10 3.75 B 8.00±0.10 0.15(4X) SEATING PLANE C 51-85178-** MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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® CY62167DV18 MoBL Document History Page ® Document Title: CY62167DV18 MoBL , 16-Mbit (1M x 16) Static RAM Document Number: 38-05326 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 118406 09/30/02 GUG New Data Sheet *A 123690 02/11/03 DPM Changed Advance to Preliminary Added package diagram *B 126554 04/25/03 DPM Minor Change: Changed sunset owner from DPM to HRT *C 1015643 See ECN VKN Converted from preliminary to final Removed “L” parts Removed 70 ns speed bin Updated footn
