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HD151TS207SS
Mother Board Clock Generator
for Intel P4+ Chipset (Springdale)
REJ03D0006-0100Z
Preliminary
Rev.1.00
Apr.25.2003
Description
The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock
®
generator. It is specifically designed for Intel Pentium 4+ chipset.
Features
• 3 differential pairs of current mode control CPU clocks
• 1 differential pair of Serial Reference Clock (SRC), selectable 100 MHz/200 MHz
• 6 copies PCI clocks and 3 copies PCIF
Resumo do conteúdo contido na página número 2
HD151TS207SS Key Specifications • Supply Voltages: VDD = 3.3 V±5% • CPU clock cycle to cycle jitter = |125ps| (SSC Disabled) • CPU clock group Skew = 100ps • 3V66 clock group Skew = 250psmax • PCI clock group Skew = 500psmax Rev.1.00, Apr.25.2003, page 2 of 38
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HD151TS207SS Pin Arrangement FS_B REF0 1 56 REF1 2 55 VDD_A VDD_REF 54 3 VSS_A XTAL_IN 53 VSS_IREF 4 XTAL_OUT 5 52 IREF VSS_REF 6 51 FS_A FS2/PCIF_0 7 50 TEST_CLK# FS4/PCIF_1 8 49 PCI_STOP# PCIF_2 9 48 VDD_CPU VDD_PCI 10 47 CPU_2 46 VSS_PCI 11 CPU_2# MODE/PCI_0 12 45 VSS_CPU PCI_1 13 44 CPU_1 PCI_2 14 43 CPU_1# 42 PCI_3 15 VDD_CPU VDD_PCI 16 41 CPU_0 VSS_PCI 17 40 CPU_0# SEL100_200/PCI_4 39 18 VSS_SRC 19 38 SEL33_25/PCI_5 SRC PCI_6 20 37 SRC# 21 VDD_SRC PWRDWN#/SAFE_F# 36 22 3V66_0/RESET# 35 VTT
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HD151TS207SS Pin Descriptions Pin name No. Type Description VSS_A 54 Ground Ground for PLL VSS_CPU 45 Ground for outputs VSS_IREF 53 Ground for current reference VSS_SRC 39 Ground for outputs VSS_3V66 25 VSS_PCI 11, 17 VSS_REF 6 VSS_48 33 VDD_A 55 Power 3.3 V Power Supply for PLL VDD_CPU 42, 48 3.3 V Power Supply for outputs VDD_SRC 36 VDD_3V66 24 VDD_PCI 10, 16 VDD_REF 3 VDD_48 34 REF0 1 OUTPUT 3.3 V 14.318 MHz reference clock. REF1 2 XTAL_IN 4 INPUT 14.318 MHz XTAL input. XTAL_OUT 5 OUTPUT 14.
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HD151TS207SS Pin Descriptions (cont.) Pin name No. Type Description PWRDWN#/ 21 INPUT PWRDWN# / SAFE_F# selectable input. SAFE_F# PULL–UP* Default is PWRDWN# input. Byte15[5] = “1” : SAFE_F# input. PWRDWN# is all clocks stop pin. Asynchronous active “Low” input. When asserted low, all output clocks are disabled. SAFE_F# is active “Low” input. When SAFE_F# is “Low” ,frequency mode is changed to the predefined frequency mode. 3V66_0/RESET# 22 OUTPUT 3V66 / Watchdog RESET# selectable output. Defaul
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HD151TS207SS Block Diagram 3.3 V VDD_48 VSS_48 3.3 V VDD_A VSS_A 6× 3.3V VDD 6×VSS VSS_IREF IREF REF[1:0] (14.318MHz) XTAL 14.318 MHz CK2 1/M2 CPU[2:0] OSC CPU[2:0]# PLL2 VCO2 SSC2 For SRC CPU SRC# 1/N2 Clock PCI[6:0] PWRDWN#/SAFE_F# Select PCIF[2:0] CK1 Input PCI_STOP# 1/M1 PLL1 Clock For VTT_PWRGD# Clock Select VCO1 Delay SRC SSC1 Divider 3V66_0/RESET# Control 3V66 3V66[3:1] PCI Stop 1/N1 Control 3V66_4/VCH TEST_CLK# CK0 1/M0 *MODE VCO0 USB *SEL100_200 USB_48 *SEL66_48 PLL 1/N0 *SEL48_24 DO
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HD151TS207SS 2 I C Controlled Register Bit Map Byte0 Control Register Bit Description Contents Type Default Note 7 Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 PCI_Stop Reflects the current value 0 = PCI_STOP# pin is Low RX of the external PCI_STOP# pin 1 = PCI_STOP# pin is High 2 Reserved R X 1 FS_B Reflects the value of the 0 = FS_B Low at power up RX See FS_B pin sampled on power up 1 = FS_B High at power up Table 1 0 FS_A Reflects the value of the 0 = FS_A Low at power up RX F
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Table3 FS_A and FS_B pin Input level Logic Level Min Voltage Max Voltage 0 (Low) 0.35V 1 (High) 0.70V Byte1 Control Register Bit Description Contents Type Default Note 7 Allow control of SCR with assertion 0 = Free running RW 0 See of PCI_STOP# 1 = Stopped with Table5 PCI_STOP# 6 SRC Output enable 0 = Disabled (tristate) RW 1 1 = Enabled 5 Reserved RW 1 4 Reserved RW 1 3 Reserved RW 1 2 CPU2 Output enable 0 = Disabled (tristate) RW 1 1 =
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Table4 CPU Clock Power Management Truth Table Signal Pin PWRDWN# Non-Stop Note PWRDWN# Tristate Bit Outputs Byte2[5:3] Byte1[5:3] = 1 CPU[2:0] 1 X Running CPU[2:0] 0 0 Driven @ Iref x2 See Note1 CPU[2:0] 0 1 Tristate Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA, Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω ) Table5 SRC Clock Power Management Truth Table Signal Pin Pin PCI_STOP# PWRDWN# Non-Stop Stoppable Note PWRDWN# PCI_STOP# Tristate Bit Tr
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte4 Control Register Bit Description Contents Type Default Note 7 USB_48 2x output drive 0 = 2x Drive strength, RW 0 1 = Normal 6 USB_48MHz Output Enable 0 = Disabled, RW 1 1 = Enabled 5 Allow control of PCIF_2 with 0 = Free Running RW 0 assertion of PCI_STOP# 1 = Stopped with PCI_STOP# 4 Allow control of PCIF_1 with 0 = Free Running RW 0 assertion of PCI_STOP# 1 = Stopped with PCI_STOP# 3 Allow control of PCIF_0 with 0 = Free Running RW 0
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte7 Vendor Identification Register Bit Description Contents Type Default Note 7 Revision Code Bit3 Vendor Specific R 0 6 Revision Code Bit2 Vendor Specific R 0 5 Revision Code Bit1 Vendor Specific R 0 4 Revision Code Bit0 Vendor Specific R 1 3 Vendor ID Bit3 Vendor Specific R 1 2 Vendor ID Bit2 Vendor Specific R 1 1 Vendor ID Bit1 Vendor Specific R 1 0 Vendor ID Bit0 Vendor Specific R 1 Byte8 Read Back Byte Count Register Bit Description C
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte9 Control Register Bit Description Contents Type Default Note 7 SSC2 Enable Bit B6[2] = 0 or B9[7] = 1 : SSC2 =OFF RW 0 B6[2] = 1 & B9[7] = 0 : SSC2 = ON 6 SSC1 Enable Bit B6[2] = 0 or B9[6] = 1 : SSC1 = OFF RW 0 B6[2] = 1 & B9[6] = 0 : SSC1 = ON 5 Clock Frequency Control Latched input PCIF_1 at Power ON RW X See Bit4 Table 6 4 Clock Frequency Control Latched input DOT48 at Power ON RW X Bit3 3 Clock Frequency Control Latched input PCI
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Table6 Clock Frequency Function Table No. FS_4 FS_3 FS_2 FS_A FS_B CPU SRC 3V66 PCI [MHz] [MHz] [MHz] [MHz] B9[5] B9[4] B9[3] B9[2] B9[1] 0 0 0 0 0 0 100.02 100.02 66.68 33.34 1 0 0 0 0 1 200.03 100.02 66.68 33.34 2 0 0 0 1 0 133.36 100.02 66.68 33.34 3 0 0 0 1 1 166.69 100.02 66.68 33.34 4 0 0 1 0 0 200.03 100.02 66.68 33.34 5 0 0 1 0 1 400.07 100.02 66.68 33.34 6 0 0 1 1 0 266.71 100.02 66.68 33.34 7 0 0 1 1 1 333.39 100.02 66.68 33.34 8 0
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte10 Control Register Bit Description Contents Type Default Note 7 SSC Spread Select Bit[2:0] Bit[2:0] = RW 0 000 = –0.500%, 100 = ±0.250% 6 RW 0 001 = –0.750%, 101 = ±0.375% 5 RW 0 010 = –1.000%, 110 = ±0.500% 011 = –1.500%, 111 = ±0.750% 4 Backup of latch Input FS_4 at When SAFE_F# is Enable RX Power ON (B15[5]=1) PWRDWN#/SAFE_F# pin to 3 Backup of latch Input FS_3 at RX “Low”, and if B23[1]=0, frequency Power ON selection is changed to
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte12 Control Register Bit Description Contents Type Default Note 7 Reserved R/W 0 6 Reserved R/W 0 5 Reserved R/W 0 4 Reserved R/W 0 3 Reserved R/W 0 2 PLL1 Output (VCO1) Frequency 0 = Normal mode R/W 0 See. Control Bit PLL1 M1[6:0] and N1[9:0] are Note (M1/N1 Divider Control Bit) changed on Table 5 selection 1 PLL1 : for SRC/3V66/PCI_PLL decided by FS4/3/2/A/B or B9[5:1] 1 = Over or Down clocking mode PLL1 M1[6:0] and N1[9:0] are changed
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte14 Control Register Bit Description Contents Type Default Note 7 Reserved R/W 0 See Note 6 PLL1 M1 Divider Control Bit6 M1[6] R/W 0 1 5 PLL1 M1 Divider Control Bit5 M1[5] R/W 0 4 PLL1 M1 Divider Control Bit4 M1[4] R/W 1 3 PLL1 M1 Divider Control Bit3 M1[3] R/W 0 2 PLL1 M1 Divider Control Bit2 M1[2] R/W 0 1 PLL1 M1 Divider Control Bit1 M1[1] R/W 1 0 PLL1 M1 Divider Control Bit0 M1[0] R/W 0 Note: 1. B12[1:0], B13[7:0] and B14[6:0] must be
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte16 Control Register Bit Description Contents Type Default Note 7 3V66 / PCI / PCIF Divider Control 3V66 divider ratio = R/W X Bit3 0010 = 1/2, 0111 = 1/7 0011 = 1/3, 1000 = 1/8 6 3V66 / PCI / PCIF Divider Control R/W X 0100 = 1/4, 1001 = 1/9 Bit2 0101 = 1/5, 1010 = 1/10 0110 = 1/6, 1011 = 1/11 5 3V66 / PCI / PCIF Divider Control PCI / PCIF divider ratio = 3v66 x R/W X Bit1 1/2 4 3V66 / PCI / PCIF Divider Control R/W X Bit0 3 SRC Divider
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte18 Control Register Bit Description Contents Type Default Note 7 VCO2 Frequency Control Bit7 These bits are 10MHz digit of R/W 0 See VCO2 frequency. Note 6 VCO2 Frequency Control Bit6 R/W 0 0000 = 0, 0001 = 1 …. 1001 = 9 1 5 VCO2 Frequency Control Bit5 R/W 0 4 VCO2 Frequency Control Bit4 R/W 0 3 VCO2 Frequency Control Bit3 These bits are 1MHz digit of R/W 0 VCO2 frequency. 2 VCO2 Frequency Control Bit2 R/W 0 0000 = 0, 0001 = 1 …. 1001 =
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte19 Control Register Bit Description Contents Type Default Note 7 VCO2 Frequency Read Bit15 Calculation result of VCO2 R 0 frequency. 6 VCO2 Frequency Read Bit14 R 0 100 MHz digit 5 VCO2 Frequency Read Bit13 R 0 0000 = 0, 0001 = 1 …. 1001 = 9 4 VCO2 Frequency Read Bit12 R0 3 VCO2 Frequency Read Bit11 Calculation result of VCO2 R 0 frequency. 2 VCO2 Frequency Read Bit10 R 0 10 MHz digit 1 VCO2 Frequency Read Bit9 R 0 0000 = 0, 0001 = 1 ….
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HD151TS207SS 2 I C Controlled Register Bit Map (cont.) Byte22 Control Register Bit Description Contents Type Default Note 7 CPU Frequency Read Bit7 Calculation result of CPU frequency. R 0 1 MHz digit 6 CPU Frequency Read Bit6 R 0 0000 = 0, 0001 = 1 …. 1001 = 9 5 CPU Frequency Read Bit5 R 0 4 CPU Frequency Read Bit4 R0 3 CPU Frequency Read Bit3 Calculation result of CPU frequency. R 0 0.1 MHz digit 2 CPU Frequency Read Bit2 R 0 0000 = 0, 0001 = 1 …. 1001 = 9 1 CPU Frequency Read Bit1 R 0 0 CPU F
