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DSP56364 24-Bit Digital Signal
Processor
Users Manual
Document Number: DSP56364UM
Rev. 2
08/2006
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How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted Home Page: hereunder to design or fabricate any integrated circuits or integrated circuits based on the information www.freescale.com in this document. E-mail: Freescale Semiconductor reserves the right to make changes without further notice to any products support@freescale.com herein.
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Contents Manual Conventions 1 Overview 1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Audio Processor Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 Core Description
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3 Memory Configuration 3.1 Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1.1 Program RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1.2 Program ROM. . . . . . . . . . . . . . . . . . . . .
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5 General Purpose Input/Output Port (GPIO) 5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 GPIO Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2.1 Port B Control Register (PCRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1.1 PCRB Control Bits (PC[3:0]) - B
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6.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.3.2.8 TCR Transmit Word Ali
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6.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.4 SAICR Reserved Bits - Bits 3-5, 9-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.5 SA
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6.6.2 Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.6.3 Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 7 Serial Host Interface 7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Serial Host Interface Internal Architecture. . . . . . . . . . . . .
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2 7.6.2 I C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.7 SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.7.1 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.7.2 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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BookTitle, Rev. # x Freescale Semiconductor
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List of Figures Figure 1-1 DSP56364 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 3-1 Memory Maps for MS=0, SC=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Figure 3-2 Memory Maps for MS=1, SC=0 . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure C-2 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 Figure C-3 Interrupt Priority Register-Core (IPR-C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 Figure C-4 Interrupt Priority Register- Peripherals (IPR-P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12 Figure C-5 Phase Lock Loop Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13
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List of Tables Table 2-1 DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Table 2-3 Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Table 2-4 Clock and PLL Signals . . . . . . . . . . . . . . . . . . .
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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2 xiv Freescale Semiconductor
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Preface This manual contains the following sections and appendices. SECTION 1—DSP56364 OVERVIEW • Provides a brief description of the DSP56364, including a features list and block diagram. Lists related documentation needed to use this chip and describes the organization of this manual. SECTION 2—SIGNAL/CONNECTION DESCRIPTIONS • Describes the signals on the DSP56364 pins and how these signals are grouped into interfaces. SECTION 3—MEMORY CONFIGURATION • Describes the DSP56364 memory spaces, RAM
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Manual Conventions The following conventions are used in this manual: • Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). • When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer’s sheets to see the exact location of
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— the reset instruction, written as “RESET,” — the reset operating state, written as “Reset,” and — the reset function, written as “reset.” DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2 Freescale Semiconductor xvii
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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2 xviii Freescale Semiconductor
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1 Overview 1.1 Introduction The DSP56364 24-Bit Digital Signal Processor, a new audio digital signal processor based on the 24-bit DSP56300 architecture, is targeted to applications that require digital audio signal processing such as sound field processing, acoustic equalization and other digital audio algorithms. The DSP56364 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56364 uses the high performance
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Features 4 12 5 PROGRAM X Y ME M O R Y RAM MEMOR Y RAM GPIO ESAI SHI 0.5K x 24 RAM 1.5K X 24 PROGRAM ROM 1K X 2 4 8K x 24 Bootstr ap R O M PERIPHERAL 192 x 24 MEMOR Y EXP ANSION EXP ANSION AREA AREA ADDRESS ADDRESS YAB EXTERNAL GE NERA T ION UNIT XAB 18 AD DR ESS B U S PAB SIX CH AN NELS DAB SWITCH DM A UN IT 24-BIT CONTROL DR AM & SR AM 6 DSP56300 BUS INTERF ACE CORE DDB YDB DATA EXTERNAL INTERNAL 8 DA T A B U S D A T A B U S XDB SWITCH SWITCH PDB GDB POWER MGMT D A T
