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TMS320 SECOND-GENERATION
DIGITAL SIGNAL PROCESSORS
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
†
68-Pin GB Package
• 80-ns Instruction Cycle Time
(Top View)
• 544 Words of On-Chip Data RAM 12345678 9 1011
• 4K Words of On-Chip Secure Program A
EPROM (TMS320E25)
B
C
• 4K Words of On-Chip Program ROM
D
(TMS320C25)
E
• 128K Words of Data/Program Space
F
• 32-Bit ALU/Accumulator
G
H
• 16 × 16-Bit Multiplier With a 32-Bit Product
J
• Block Moves for Data/Program
K
Management
L
• Repeat Instructio
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN A0 K1/26 A12 K8/40 D2 E1/16 D14 A5/3 INT2 H1/22 V H2/23 CC A1 K2/28 A13 L9/41 D3 D2/15 D15 B6/2 IS J11/46 V L6/35 CC † A2 L3/29 A14 K9/42 D4 D1/14 DR J1/24 MP/MC A6/1 V B1/10 SS A3 K3/30 A15 L10/43 D5 C2/13 DS K10/45 MSC C10/59 V K11/44 SS A4 L4/31 BIO B7/68 D6 C1/12 DX E11/54 PS J10/47 V L2/27 SS A5 K4/32
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 description The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a MOS microprocessor family that is capable of
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Key Features: TMS32020 +5 V GND • 200-ns Instruction Cycle Time • 544 Words of On-Chip Data RAM Interrupts 256-Word 288-Word • 128K Words of Total Data/Program Data (16) Data/Prog Data Memory Space RAM RAM Multi- • Wait States for Communication to Slower Off-Chip Processor Multiplier Memories Interface • Source Code Compatible With the TMS320C1x Serial 32-BIT ALU/ACC Interface • Single-Cycle Multiply/Accumulate Instruct
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 1 provides an overview of the second-generation TMS320 processors with comparisons of memory, I/O, cycle timing, power, package type, technology, and military support. For specific availability, contact the nearest TI Field Sales Office. Table 1. TMS320 Second-Generation Device Overview MEMORY PACKAGE CYCLE TYP † I/O TYPE ON-CHIP OFF-CHIP TIME POWER DEVICE TIMER (ns) (mW) RAM ROM/EPROM PROG DATA SER PAR DMA P
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) SYNC Program Bus IS DS PS 16 16 16 16 PFC(16) QIR(16) R/W IR(16) STRB 16 READY STO(16) MUX BR ST1(16) 16 XF RPTC(8) 16 16 HOLD HOLDA IFR(6) MCS(16) PC(16) MSC DR BIO CLKR RS FSR 16 16 16 DX IACK CLKX Address Stack FSX 16 16 MP/MC 16 3 (8 x 16) RSR(16) Program INT(2-0) ROM/ XSR(16) 16 EPROM 16 16 DRR(16) (4096 × 16) A15-A0 16 DXR(16) 16 Instruction TIM(16) 16 PRD(16) 16 6 IMR(6) 16 16
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 scaling shifter The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Program Program Data 0(0000h) 0(0000h) 0(0000h) Interrupts Interrupts On-Chip and Reserved and Reserved Memory-Mapped (On-Chip (External) Registers ROM/EPROM) 31(001Fh) 5(0005h) 31(001Fh) 32(0020h ) 6(0006h) 32(0020h ) Page 0 Reserved On-Chip ROM/EPROM 95(005Fh) 4015(0FAFh) 96(0060h ) 4016(0FB0h) On-Chip Block B2 127(007Fh) Reserved 128(0080h) 4095(0FFFh) Pages 1-3 Reserved 4096(1000h) 511(01FFh) 512(0200h) External On
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 interrupts and subroutines The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest priority and the serial port transmit interrupt (XINT) hav
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 instruction set The TMS320C2x microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25 source code. TMS32020 object code runs directly on the TMS320C25. For maximum throughput, the next instruction is prefe
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 instruction set summary Table 2 lists the symbols and abbreviations used in Table 3, the TMS320C25 instruction set summary. Table 3 consists primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions are multicycle. The instruction set summary is arranged according to function and alphabetized within each † functional grouping. The symbol ( ) indicates those instructio
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TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS INSTRUCTION BIT CODE NO. MNEMONIC DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABS Absolute value of accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1 ADD Add to accumulator with shift 1 0 00 0 I D S ‡ ADDC Add to accumulator with carry 1 0 10 000 1 1 I D ADDH Add to high accumulator 1 0 10 010 0 0 I D ‡ ADDK Add to accumulator short immediate 1 1 10 0
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TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (continued) ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS INSTRUCTION BIT CODE NO. MNEMONIC DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Subtract from accumulator with shift specified by † SUBT 1 0 1 0 0 0 1 1 0 I D T register XOR Exclusive-OR with accumulator 1 0 10 011 0 0 I D Exclusive-OR immediate with accumulator with † XORK 2 1 1 0 1 0 00 00 11 0 S shift ZAC Zero accumulator 1 1 10
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TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (continued) T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS INSTRUCTION BIT CODE NO. MNEMONIC DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 APAC Add P register to accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 † LPH Load high P register 1 0 10 100 1 1 I D LT Load T register 1 0 01 111 0 0 I D LTA Load T register and accumulate previous product 1 0 01 111 0 1 I D Load T register, accumulate
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TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (continued) BRANCH/CALL INSTRUCTIONS INSTRUCTION BIT CODE NO. MNEMONIC DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B Branch unconditionally 2 1 1 1 1 1 1 1 1 1 D † BACC Branch to address specified by accumulator 1 1 100 11 1 0 0 0 1 0 0 1 0 1 BANZ Branch on auxiliary register not zero 2 1 111 10 1 1 1 D † BBNZ Branch if TC bit ≠ 02 1 111 10 0 1 1 D † BBZ Branch if TC bit = 0 2 1 11
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TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 3. TMS320C25 Instruction Set Summary (concluded) CONTROL INSTRUCTIONS INSTRUCTION BIT CODE NO. MNEMONIC DESCRIPTION WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 † BIT Test bit 1 1 0 0 1 I B D † BITT Test bit specified by T register 1 0 10 101 1 1 I D † CNFD Configure block as data memory 1 1 10 011 1 0 0 0 0 0 0 1 0 0 † CNFP Configure block as program memory 1 1 10 011 1 0 0 0 0 0 0 1 0 1 DINT Disable interrupt 1 1 10 011 1 0 0 0 0 0 0 0
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TMS32020 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 TMS32020 PRODUCT NOTIFICATION Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the accumulator. This set of conditions is: 1. The overflow mode is set (the OVM status register bit is set to one.) 2. And, the two LSBs of the BIT instruction opcode word are zero. a. When di
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 development support Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development support products to assist the user in all aspects of TMS320 second-generation-based design and development. These products range from development and application software to complete hardware development and evaluation systems. Table 4 lists the development support products for the second-gene
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 Table 4. TMS320 Second-Generation Software and Hardware Support SOFTWARE TOOLS PART NUMBER Macro Assembler/Linker IBM MS/PC-DOS TMDS3242850-02 VAX/VMS TMDS3242250-08 VAX ULTRIX TMDS3242260-08 SUN UNIX TMDS3242550-08 Simulator IBM MS/PC-DOS TMDS3242851-02 VAX/VMS TMDS3242251-08 C Compiler IBM MS/PC-DOS TMDX3242855-02 VAX/VMS TMDX3242255-08 VAX ULTRIX TMDX3242265-08 SUN UNIX TMDX3242555-08 Digital Filter Design Packa
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TMS320 SECOND-GENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 documentation support Extensive documentation supports the second-generation TMS320 devices from product announcement through applications development. The types of documentation include data sheets with design specifications, complete user’s guides, and 750 pages of application reports published in the book, Digital Signal Processing Applications with the TMS320 Family (SPRA012A). An application report, Hardware Interf
