Manual do usuário Fujitsu CS81

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CS81 Series Standard Cell
0.18μm CMOS Technology
CS81 I/O Interface Capabilities
Features
t
• 0.13μm effective channel length
PLL High-Speed
1.8V CMOS
1.8V
T-LVTTL
1.8V Device
Interface
• 3 to 5 layers of metal interconnects Clock Input
CMOS
P-CML
High-Speed
2
Devices
• Very high density: 110K raw gates/mm LVDS
SSTL
2.5V CMOS
2.5V
• Up to 28 million gates
2.5V Device
CS81
CMOS HSTL
Analog
• Core power supply voltage: 1.8V to 1.1V
(1.8V)
Interface
• 5 nW/gate/MHz power dissipation at 1.1V

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CS81 Series Standard Cell predicts performance in advance. Fujitsu supports co-sim- Phase-Locked Loops ulation, emulation and high-level floor-planning to opti- • Analog: up to 800 MHz mize the power, timing, and size of the design. This I/Os enables the designer to make effective architectural-level • 1.8V, 2.5V, and 3.3V CMOS (2.5V is under decisions to achieve optimal design solutions. development) Fujitsu’s design methodology supports cycle-based simula- • Slew-rate controlled tors and

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0.18μm CMOS Technology PACKAGE AVAILABILITY No. of Pins/Balls Pin/Ball Pitch Dimensions TAB-BGA (Cavity-down) 304 0.8 mm 21 mm 352 0.8 mm 23 mm 480 1.0 mm 31 mm 560 1.0 mm 35 mm 660 1.0 mm 40 mm 720 1.0 mm 40 mm EBGA (Cavity-down) 576 1.27 mm 40 mm 672 1.27 mm 45 mm HQFP (Cavity-up) 208 0.50 mm 28 mm 240 0.50 mm 32 mm 256 0.40 mm 28 mm 304 0.50 mm 40 mm TQFP (Cavity-up) 100 0.50 mm 14 mm 120 0.50 mm 20 mm LQFP (Cavity-up) 144 0.50 mm 20 mm 176 0.50 mm 24 mm 208 0.50 mm 28 mm FBGA (C

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FUJITSU MICROELECTRONICS AMERICA, INC. Corporate Headquarters © 1999 Fujitsu Microelectronics, Inc. 1250 East Arques Avenue, Sunnyvale, California 94088-3470 All company and product names are trademarks or Tel: (800) 866-8608 Fax: (408) 737-5999 registered trademarks of their respective owners. E-mail: inquiry@fma.fujitsu.com Internet: http://www.fma.fujitsu.com Printed in the U.S.A. ASIC-FS-20820-10/99