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MSP50C6xx Mixed-Signal Processor
User’s Guide
Mixed Signal Products
SPSU014A
Printed on Recycled Paper
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infri
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Preface Read This First About This Manual This user’s guide gives information for the MSP50C6xx mixed-signal proces- sor. This information includes a functional overview, a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications, customer informa- tion, and electrical characteristics (in data sheet). How to Use This Manual This document contains the following chapters: Chapter 1 –Introduction to t
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Notational Conventions Here is a sample program listing: 0011 0005 0001 .field 1, 2 0012 0005 0003 .field 3, 4 0013 0005 0006 .field 6, 3 0014 0006 .even Here is an example of a system prompt and a command that you might enter: C: csr –a /user/ti/simuboard/utilities In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface. Portions of a syntax that are in bold should
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Information About Cautions and Warnings .byte value [, ... , value ] 1 n This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas. Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement.
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vi
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Contents Contents 1 Introduction to the MSP50C6xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Features of the MSP50C6xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Development Device: MSP50P614 . . . . . . . . . . . . . . .
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Contents 3 Peripheral Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Dedicated Input Port F . . . . . . . . . . . . . . . . . .
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Contents 4.4 Instruction Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.4.2 Class 2 Instructions: Accumulator and Constant Reference . . . . . . . . . . . . . . 4-28 4.4.3 Class 3 Instruction: Accumulator Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.4.4 Class 4 Instructions: Address Register and Memory Reference . . . . . . . . . . . 4-34 4.4.5 Class 5 Instructions: Memory Reference . . . .
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Contents 5.6 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.1 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.2 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.6.3 Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures Figures 1–1 Functional Block Diagram for the MSP50C614/MSP50P614 . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1–2 Oscillator and PLL Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1–3 RESET Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 2–1 MSP50C6xx Core Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . .
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Tables Tables 2–1 Signed and Unsigned Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2–2 Summary of MSP50C614’s Peripheral Communications Ports . . . . . . . . . . . . . . . . . . . . . 2-17 2–3 Programmable Bits Needed to Control Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . 2-36 2–4 Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3) . . . . . . . . . . . . 2-37 2–5 How to Wake Up from Reduced Power Modes (R
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Tables 4–28 Class 6a Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4–29 Class 6a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4–30 Class 6b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 4–31 Class 7 Instruction Encoding and Description . . . . . . . . . . . . . .
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Chapter 1 Introduction to the MSP50C6xx The MSP50C6xx is a low cost, mixed signal controller, that combines a speech synthesizer, general-purpose input/output (I/O), onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the MSP50C6xx unprecedented speed and computational flexibility compared with previous devices of its type. The MSP50C6xx supports a variety of speech and audio coding algorithms, providing a range of options wit
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Features of the MSP50C6xx 1.1 Features of the MSP50C6xx Advanced, integrated speech synthesizer for high quality sound Operates up to 12.32 MHz (performs up to 12.32 MIPS) Very low-power operation, ideal for hand-held devices Low voltage operation, sustainable by three batteries Reduced power stand-by modes, less than 10 µ A in deep-sleep mode Supports high-quality synthesis algorithms such as MELP, CELP, LPC, and ADPCM Contains 32K words onboard ROM (2K words reserved) Up to 2.3
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Applications 1.2 Applications Due to its low cost, low-power consumption, and high programmability, the MSP50C6xx is suitable for a wide variety of applications incorporating flexible I/O and high-quality speech: Consumer Education Toys and Games Electronic Learning Aids Appliances Talking Dictionaries Talking Clocks Language Translators Navigation Aids Talking Books Industrial Medical Warning Systems Controls Aids for the Handicapped Telecom Security Answering Machines Security Syst
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Development Device: MSP50P614 1.3 Development Device: MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614, and is available in a 120-pin windowed ceramic pin grid array. This EPROM based version of the device is only available in limited quantities to support software development. Since the MSP50P614 program memory is EPROM, each person doing software development should have several of these PGA packaged devices. The MSP50P614 is also used to emulate the MSP50C601, MSP50C604, and
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Functional Description for the MSP50C614 1.4 Functional Description for the MSP50C614 The MSP50C614 device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-pur- pose periphery is comprised of 64 bits of flexible I/O. The block diagram ap- pearing in Figure 1–1 gives an overview of the MSP50C614/MSP50P614 functionality. Figure 1–1. Functional Block Diagram for the MSP50C614/MSP50P614 V V V SS DD PP 55 Power (P614 only) A port
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Functional Description for the MSP50C614 The core processor is a general-purpose 16 bit micro-controller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor, and several system and control registers. The core processor provides break-point capability to the MSP50C6xx code development software (EMUC6xx). The processor is a Harvard type for efficient DSP algorithm execution. It re- quires
