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LPC2917/19
ARM9 microcontroller with CAN and LIN
Rev. 1.01 — 15 November 2007 Preliminary data sheet
1. Introduction
1.1 About this document
This document lists detailed information about the LPC2917/19 device. It focuses on
factual information like pinning, characteristics etc. Short descriptions are used to outline
the concept of the features and functions. More details and
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN 2.2 ARM968E-S processor The ARM968E-S is a general purpose 32-bit RISC processor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN 2.4 On-chip static RAM In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one of 32 kB and one of 16 kB. Both may be used for code and/or data storage. Each internal SRAM has its own controller, so both memories can be accessed simultaneously from different AHB system bus layers.
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Highly configurable system Power Management Unit (PMU), clock control of individual modules allows minimization of system operating power consumption in any configuration Standard ARM test and debug interface with real-time in-circuit emulator Boundary-scan test supported Dual power supply: CPU operating v
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN 5. Block diagram ITCM DTCM ARM968E-S LPC2917/19 16 Kb 16 Kb s m IEEE 1149.1 JTAG TEST and s Vectored Interrupt DEBUG INTERFACE Controller (VIC) s External Static Memory Embedded Controller (SMC) FLASH Memory 512/768 Kb s Embedded FLASH Memory Controller (FMC) SRAM Memory 16 Kb s SRAM Controller #1 Modulation and
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN 6. Pinning information 6.1 Pinning 1 108 LPC2917FBD144 LPC2919FBD144 36 73 144PINS Fig 2. Pin configuration for SOT486-1 (LQFP144) 6.2 Pin description 6.2.1 General description The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16 pins. The pin to which each function is assigned
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 3. LQFP144 pin assignment …continued Symbol Pin Description Function 0 (default) Function 1 Function 2 Function 3 P2.24 16 GPIO 2, pin 24 - PWM3 CAP1 EXTBUS D22 P2.25 17 GPIO 2, pin 25 - PWM3 CAP2 EXTBUS D23 V 18 1.8 V power supply for digital core DD(CORE) V 19 ground for digital core SS(CORE) P1.31 20 GPI
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 3. LQFP144 pin assignment …continued Symbol Pin Description Function 0 (default) Function 1 Function 2 Function 3 V 53 3.3 V power supply for I/O DD(IO) P2.2 54 GPIO 2, pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10 P2.3 55 GPIO 2, pin 3 TIMER2 MAT3 PWM TRAP0 EXTBUS D11 P1.11 56 GPIO 1, pin 11 SPI1 SCK - EXTBUS CS3
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 3. LQFP144 pin assignment …continued Symbol Pin Description Function 0 (default) Function 1 Function 2 Function 3 P0.0 93 GPIO 0, pin 0 - CAN0 TxD EXTBUS D24 V 94 ground for I/O SS(IO) P0.1 95 GPIO 0, pin 1 - CAN0 RxD EXTBUS D25 P0.2 96 GPIO 0, pin 2 - PWM0 MAT0 EXTBUS D26 P0.3 97 GPIO 0, pin 3 - PWM0 MAT1
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 3. LQFP144 pin assignment …continued Symbol Pin Description Function 0 (default) Function 1 Function 2 Function 3 P0.18 132 GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14 P0.19 133 GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15 P3.4 134 GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TxD P3.5 135 GPIO 3, pin 5 TIMER3
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN 7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test) The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can be used to connect a debugger probe for the embedded ARM processor. Pin JTAGS
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN ITCM DTCM ARM968E-S LPC2917/19 16 Kb 16 Kb s m SYS_CLK IEEE 1149.1 JTAG TEST and s Vectored Interrupt DEBUG INTERFACE Controller (VIC) s External Static Memory Embedded Controller (SMC) FLASH Memory 512 - 768 Kb s Embedded FLASH Memory Controller (FMC) SRAM Memory 16 Kb s SRAM Controller #1 Modulation and Sampli
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN 7.2.2 Base clock and branch clock relationship The next table contains an overview of all the base blocks in the LPC2917/19 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be f
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 7. Base clock and branch clock overview …continued Base clock Branch clock name Parts of the device clocked by Remark this branch clock BASE_MSCSS_CLK CLK_MSCSS_VPB VPB side of the MSCSS CLK_MSCSS_MTMR0 Timer 0 in the MSCSS CLK_MSCSS_MTMR1 Timer 1 in the MSCSS CLK_MSCSS_PWM0 PWM 0 CLK_MSCSS_PWM1 PWM 0 CLK_MS
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the boot loader. In-application programming is possible. Flash memory contents
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Both buffer lines are invalidated after: • Initialization • Configuration-register access • Data-latch reading • Index-sector reading The modes of operation are listed in Table 8. Table 8. Flash read modes Synchronous timing No buffer line for single (non-linear) reads; one flash-word read per word read Single b
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 9. Flash sector overview …continued Sector number Sector size (kB) Sector base address 3 8 0000 6000h 4 8 0000 8000h 5 8 0000 A000h 6 8 0000 C000h 7 8 0000 E000h 8 64 0001 0000h 9 64 0002 0000h 10 64 0003 0000h 11 64 0004 0000h 12 64 0005 0000h 13 64 0006 0000h 14 64 0007 0000h [1] 15 64 0008 0000h [1] 16 64
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. 8.2 External static memory controller 8.2.1 Overview The LPC2917/19 contains an external Static Memory Controller
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN Table 11. External static-memory controller banks CS[2:0] Bank 000 bank 0 001 bank 1 010 bank 2 011 bank 3 100 bank 4 101 bank 5 110 bank 6 111 bank 7 8.2.3 External static-memory controller pin description The external static-memory controller module in the LPC2917/19 has the following pins, which are combined
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DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRAFT DRAFT DRAFT D DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA LPC2917/19 NXP Semiconductors ARM9 microcontroller with CAN and LIN CLK(SYS) CS OE_N ADDR DATA WSTOEN WST1 WSTOEN=3, WST1=7 Fig 4. Reading from external memory A timing diagram for writing to external memory is shown In Figure 5. The relationship between wait-state settings is indicated with arrows. CLK(SYS) CS WE_N / BLS ADDR DATA WSTWEN WST2 WSTWEN=3, WST2=7 Fig 5. Writing
