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EM78P458/459
OTP ROM
EM78P458/459
8-BIT MICRO-CONTROLLER
Version 1.3
ELAN MICROELECTRONICS CORP.
st
No. 12, Innovation 1 RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03)5782037(SL) 5630118 (FAE)
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EM78P458/459 OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Modify ERC frequency 2003/03/06 1.2 Add AD & OP spec 2003/05/07 1.3 Change Power on reset content 2003/07/01 Application Note AN-001 A/D Pre-amplifier AN-002 Calibration Offset on A/D AN-003 Example of Microcomputer Digital Thermometer AN-004 Tips on how to apply EM78P458 AN-005 Tips on how to apply A/D Converter AN-006 AD & R4 AN-007 Enhancing Noise Immunity
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EM78P458/459 OTP ROM 1. GENERAL DESCRIPTION EM78P458 and EM78P459 are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. It is equipped with a 4K*13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development code. This specification is subject to chan
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EM78P458/459 OTP ROM 2. FEATURES • Operating voltage range: 2.3V~5.5V • Operating temperature range: 0 °C~70 °C • Operating frequency range(base on 2 clocks): * Crystal mode: DC ~ 20MHz/2clks,5V; DC ~ 8MHz/2clks,3V * RC mode: DC ~ 4MHz/2clks,5V; DC ~ 4MHz/2clks,3V • Low power consumption: * Less than 1.5 mA at 5V/4MHz * Typically 15 µA, at 3V/32KHz * Typically 1 µA, during sleep mode • 4K × 13 bits on chip ROM • 84 × 8 bits on chip registers (SRAM) • 2 bi-directional I/O port
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EM78P458/459 OTP ROM • Package types: * 20 pin DIP 300mil : EM78P458AP * 20 pin SOP 300mil : EM78P458AM * 24 pin skinny DIP 300mil : EM78P459AK * 24 pin SOP 300mil : EM78P459AM • Power on voltage detector available (2.0V ± 0.15V) This specification is subject to change without prior notice. 5 07.01.2003 (V1.3)
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EM78P459 EM78P458 EM78P458/459 OTP ROM 3. PIN ASSIGNMENT P56/CIN+ 1 24 P55/CIN- P57/CO 2 23 P54/TCC P60/ADC1 3 22 OSCI 20 P55/CIN- P56/CIN+ 1 P61/ADC2 4 21 OSCO P57/CO 2 19 P54/TCC ENTCC 5 20 RESET 3 18 OSCI P60/ADC1 VSS 6 19 VDD 4 17 OSCO P61/ADC2 VSS 7 18 VDD VSS 5 16 VDD P62/ADC3 8 17 P53/VREF 6 15 P53/VREF P62/ADC3 P63/ADC4 9 16 P52/PWM2 7 14 P52/PWM2 P63/ADC4 P64/ADC5 10 15 P51/PWM1 P64/ADC5 8 13 P51/PWM1 P65/ADC6 11 14 P50/INT 9 12 P50/INT P65/ADC6 P66/ADC7 12 13 P67/ADC8 10 11 P67/
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EM78P458/459 OTP ROM PWM2 * Defined by PWMCON (IOC51)<6, 7> * External reference voltage for ADC VREF 15 I * Defined by AD-CMPCON (IOCA0)<7>. * “-“ -> the input pin of Vin- of the comparator. CIN-, CIN+, I * “+”-> the input pin of Vin+ of the comparator. 20, 1,2 CO O * Pin CO is the output of the comparator. * Defined by AD-CMPCON (IOCA0) <5, 6> * Real time clock/counter with Schmitt trigger input pin; it must be tied to TCC 19 I VDD or VSS if it is not in use. VSS 5 - Ground.
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EM78P458/459 OTP ROM 4. FUNCTION DESCRIPTION WDT Timer P C STACK 0 WDT Prescaler STACK 1 Time-out STACK 2 Oscillator/ STACK 3 /INT ROM Timming STACK 4 Control STACK 5 Interrupt Instruction STACK 6 ENTCC Control Register R1(TCC) STACK 7 ALU Instruction Sleep RAM Decoder & Wake Up Control R3 ACC R4 DATA & CONTROL BUS Comparators 2 PWMs 8 ADC IOC5 IOC6 R5 R6 PPPPPPPP PPPPPPPP 55555555 66666666 01234567 01234567 Fig. 2 The Functional Block Diagram of EM78P458/459 4.1 Operational Registers
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EM78P458/459 OTP ROM • The contents of R2 are set to all "0"s upon a RESET condition. • "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. • "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. • "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of th
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EM78P458/459 OTP ROM 4. R3 (Status Register) 7 6 5 4 3 2 1 0 CMPOUT PS1 PS0 T P Z DC C • Bit 7 (CMPOUT) the result of the comparator output. • Bit 6 (PS1) ~ 5 (PS0) Page select bits. PS0~PS1 are used to select a program memory page. When executing a "JMP", "CALL", or other instructions which cause the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note t
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EM78P458/459 OTP ROM R0 00 R1 (TCC) 01 R2 (PC) STACK 0 02 R9<5> (IOCS) R3 (Status) STACK 1 03 0 1 R4 (RSR) STACK 2 04 R5 (Port 5) STACK 3 IOC50 IOC51 (PWMCON) 05 R6 (Port 6) STACK 4 IOC60 IOC61 (DT1L) 06 R7 STACK 5 IOC71 (DT1H) 07 R8 STACK 6 IOC81 (PRD1) 08 R9 (ADCON) STACK 7 IOC91 (DT2L) 09 IOC90 (GCON) RA (ADDATA) IOCA0 (AD-CMPCON) IOCA1 (DT2H) 0A RB (TMR1L) IOCB0 0B IOCB1 (PRD2) RC (TMR1H) IOCC0 IOCC1 (DL1L) 0C RD (TMR2L) IOCD0 IOCD1 (DL1H) 0D RE (TMR2H) IOCE0 IOCE1 (DL2L) 0E RF IOCF0
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EM78P458/459 OTP ROM 8. R9 (ADCON: Analog to Digital Control) 7 6 5 4 3 2 1 0 - - IOCS ADRUN ADPD ADIS2 ADIS1 ADIS0 • Bit 7:Bit 6 Unemployed, read as ‘0’; • Bit 5(IOCS): Select the Segment of IO control register. 1 = Segment 1 ( IOC51~IOCF1 ) selected; 0 = Segment 0 ( IOC50~IOCF0 ) selected; • Bit 4 (ADRUN): ADC starts to RUN. 1 = an A/D conversion is started. This bit can be set by software; 0 = reset on completion of the conversion. This bit can not be reset though software;
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EM78P458/459 OTP ROM An 8-bit general-purpose register. 13. RE A 2-bit, Bit 0 and Bit 1 register. 14. RF (Interrupt Status Register) 7 6 5 4 3 2 1 0 - CMPIF PWM2IF PWM1IF ADIF EXIF ICIF TCIF “1” means interrupt request, and “0” means no interrupt occurs. • Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software. • Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by software. • Bit 2 (EXIF) External interrupt
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EM78P458/459 OTP ROM 2. CONT (Control Register) 7 6 5 4 3 2 1 0 INTE INT TS TE PAB PSR2 PSR1 PSR0 • Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 • Bit 3 (PAB) Prescaler assignment bit. 0: TCC; 1: WDT. • Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on the TCC pin; 1: inc
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EM78P458/459 OTP ROM 4. IOC90 (GCON: I/O Configuration & Control of ADC ) 7 6 5 4 3 2 1 0 OP2E OP1E G22 G21 G20 G12 G11 G10 • Bit 7 ( OP2E ) Enable the gain amplifier which input is connected to P64 and output is connected to the 8-1 analog switch. 0 = OP2 is off ( default value ), and bypasses the input signal to the ADC; 1 = OP2 is on. • Bit 6 ( OP1E ) Enable the gain amplifier whose input is connected to P60 and output is connected to the 8-1 analog switch. 0 = OP1 is off (d
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EM78P458/459 OTP ROM 1 = The Vref of the ADC is connected to P53/VREF. • Bit 6 (CE): Comparator enable bit 0 = Comparator is off (default value); 1 = Comparator is on. • Bit 5 ( COE ): Set P57 as the output of the comparator 0 = the comparator acts as an OP if CE=1. 1 = act as a comparator if CE=1. • Bit4:Bit2 (IMS2:IMS0): Input Mode Select. ADC configuration definition bit. The following Table describes how to define the characteristic of each pin of R6. Table 3 Descri
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EM78P458/459 OTP ROM • Bit 4 (/PD4) Control bit is used to enable the pull-down of the P64 pin. • Bit 5 (/PD5) Control bit is used to enable the pull-down of the P65 pin. • Bit 6 (/PD6) Control bit is used to enable the pull-down of the P66 pin. • Bit 7 (/PD7) Control bit is used to enable the pull-down of the P67 pin. • IOCB0 register is both readable and writable. 7. IOCC0 (Open-Drain Control Register) 7 6 5 4 3 2 1 0 /OD7 /OD6 /OD5 /OD4 /OD3 /OD2 /OD1 /OD0 • Bit 0 (OD0) Control
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EM78P458/459 OTP ROM 9. IOCE0 (WDT Control Register) 7 6 5 4 3 2 1 0 WDTE EIS - - - - - - • Bit 7 (WDTE) Control bit is used to enable Watchdog Timer. 0: Disable WDT; 1: Enable WDT. WDTE is both readable and writable • Bit 6 (EIS) Control bit is used to define the function of the P50 (/INT) pin. 0: P50, input pin only; 1: /INT, external interrupt pin. In this case, the I/O control bit of P50 (bit 0 of IOC50) must be set to "1". When EIS is "0", the path of /INT is masked. When E
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EM78P458/459 OTP ROM • Bit 5 (PWM2IE) PWM2IF interrupt enable bit. 0: disable PWM2 interrupt 1: enable PWM2 interrupt • Bit 6 (CMPIE) CMPIF interrupt enable bit. 0: disable CMPIF interrupt 1: enable CMPIF interrupt • Bit 7: Unimplemented, read as ‘0’. Individual interrupt is enabled by setting its associated control bit in the IOCF0 to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 11. IOCF0 register is both readabl
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EM78P458/459 OTP ROM • Bit 1 : Bit 0 ( T1P1:T1P0 ): TMR1 clock prescale option bits. T1P1 T1P0 Prescale 0 0 1:2(Default) 0 1 1:8 1 0 1:32 1 1 1:64 12. IOC61 ( DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1 ) A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1. 13. IOC71 ( DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM1 ) 7 6 5 4 3 2 1 0 CALI1 SIGN1 VOF1[2] VOF1[1] VOF1[0] - PWM1[9] PWM1[8]
