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MVME5100
Single Board Computer
Programmer’s
Reference Guide
V5100A/PG3
July 2003 Edition
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© Copyright 2003 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola and the Motorola logo are registered trademarks and AltiVec is a trademark of Motorola, Inc. PowerPC and the PowerPC logo are registered trademarks; and PowerPC 750 is a trademark of International Business Machines Corporation and are used by Motorola, Inc. under license from International Business Machines Corporation. All other products mentioned in this document are trademarks or register
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Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessa
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Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not ! installed and used with adequate EMI protection. Caution Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry. Danger of explosion if battery i
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CE Notice (European Community) Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this directive implies conformity to the following European Norms: EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment”; this product tested to Equipment Class B EN55024 “Information technology equipment—Immunity characteristics—Limits and methods of measurement” Board products are test
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Limited and Restricted Rights Legend If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFAR
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Contents About This Manual Summary of Changes...............................................................................................xviii Overview of Contents ..............................................................................................xviii Comments and Suggestions .......................................................................................xix Conventions Used in This Manual.............................................................................xix Termi
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The Universe ASIC .......................................................................................... 1-17 PCI Configuration Space.................................................................................. 1-19 Hawk External Register Bus Address Assignments......................................... 1-21 MVME5100 Hawk External Register Bus Summary ............................... 1-21 Dual TL16C550 UARTs..................................................................................
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PCI Slave ...................................................................................................2-22 PCI FIFO ...................................................................................................2-26 PCI Master.................................................................................................2-26 Generating PCI Cycles ..............................................................................2-29 PCI Arbiter ............................................
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Interrupt Acknowledge Register ............................................................... 2-65 8259 Mode ................................................................................................ 2-65 Current Task Priority Level ...................................................................... 2-65 Architectural Notes........................................................................................... 2-66 Effects of Interrupt Serialization .................................
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Spurious Vector Register.........................................................................2-118 Timer Frequency Register .......................................................................2-118 Timer Current Count Registers................................................................2-119 Timer Basecount Registers......................................................................2-120 Timer Vector/Priority Registers ..............................................................2
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Error Logging............................................................................................ 3-13 ROM/Flash Interface........................................................................................ 3-14 ROM/Flash Speeds.................................................................................... 3-19 I2C Interface..................................................................................................... 3-22 I2C Byte Write ...................................
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Address Parity Error Log Register ............................................................3-71 Address Parity Error Address Register......................................................3-72 32-Bit Counter ...........................................................................................3-73 External Register Set .................................................................................3-73 tben Register.........................................................................
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APPENDIX B MVME5100 VPD Reference Information Vital Product Data (VPD) Introduction .................................................................... B-1 How to Read the VPD Information................................................................... B-1 How to Modify the VPD Information ............................................................... B-2 What Happens if the VPD Information is Corrupted? ...................................... B-3 How to Fix Corrupted VPD Information ........
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List of Figures Figure 1-1. MVME5100 Block Diagram...................................................................1-3 Figure 1-2. VMEbus Master Mapping.....................................................................1-18 Figure 2-1. Hawk PCI Host Bridge Block Diagram ..................................................2-3 Figure 2-2. PPC to PCI Address Decoding................................................................2-6 Figure 2-3. PPC to PCI Address Translation .....................
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List of Tables Table 1-1. MVME Key Features................................................................................1-1 Table 1-2. Default Processor Memory Map...............................................................1-4 Table 1-3. Suggested CHRP Memory Map ...............................................................1-6 Table 1-4. Hawk PPC Register Values for Suggested Memory Map.........................1-7 Table 1-5. I2C Device Addressing..........................................
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Table 2-13. Address Modification for Little Endian Transfers ............................... 2-40 Table 2-14. WDTxCNTL Programming ................................................................. 2-44 Table 2-15. PHB Hardware Configuration .............................................................. 2-50 Table 2-16. PPC Register Map for PHB.................................................................. 2-68 Table 2-17. PCI Configuration Register ............................................
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Table 4-1. MPIC Interrupt Assignments....................................................................4-1 Table 4-2. PBC ISA Interrupt Assignments...............................................................4-3 Table 4-3. Error Notification and Handling...............................................................4-6 Table A-1. Motorola Computer Group Documents .................................................A-1 Table A-2. Manufacturers’ Documents .........................................
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