Resumo do conteúdo contido na página número 1
Agilent HDMP-3001
Ethernet over SONET Mapper IC
Device Specification
Data Sheet
Table of Contents
1. Introduction ............................................................................................... 5
1.1 Internal Functional Blocks .............................................................. 5
1.2 HDMP-3001 Features List ................................................................ 5
1.3 Applications ................................................................................
Resumo do conteúdo contido na página número 2
3.9 SONET/SDH Processing................................................................. 24 3.9.1 Transmit SONET/SDH Processing Overview ...................... 24 3.9.2 Receive SONET/SDH Processing Overview ........................ 25 3.9.3 Transmit SONET/SDH Processing Details ........................... 25 3.9.4 Receive SONET/SDH Processing Details ............................. 30 4. Application Information ........................................................................ 38 4.1 Chip s
Resumo do conteúdo contido na página número 3
List of Figures Figure 1. Functional Block Diagram ......................................................... 5 Figure 2. HDMP-3001 applications ............................................................ 6 Figure 3. HDMP-3001 pin assignments ..................................................... 7 Figure 4. GFP Payload Bit Order ............................................................. 18 Figure 5. GFP FCS Bit Order .................................................................... 18 Figu
Resumo do conteúdo contido na página número 4
List of Tables Table 1. Line Side Interface Pins Description........................................... 8 Table 2. MII Interface Pins Description ..................................................... 9 Table 3. Transport Overhead Pins Description ...................................... 10 Table 4. Microprocessor Interface Pins Description ............................. 12 Table 5. JTAG Interface Pins Description ............................................... 13 Table 6. Two-Wire EEPROM Interface
Resumo do conteúdo contido na página número 5
43 1. Introduction Procedure) support which in- (X +1) polynomial for LAPS/ The Agilent HDMP-3001 is a cludes framing, 32-bit FCS GFP frames. highly integrated VLSI device that processing, 16-bit HEC process- • Link-level scrambling function provides mapping of Ethernet en- ing, and self-synchronous to improve operational capsulated packets into STS-3c scrambling/descrambling robustness. 43 payloads. The HDMP-3001 sup- (X +1). • Monitors link status when ports full-duplex processing of mapping M
Resumo do conteúdo contido na página número 6
MDIO BUS • Implemented in 0.25 micron • Ethernet switches in each LAN • IEEE 802.3 MDIO management CMOS with 1.8 V core, 3.3 V I/O can be connected together di- interface. power and LVCMOS rectly which reduces cost and • Standard 2-wire EEPROM compatible I/Os. complexity. interface for optional boot-up • Provides a 16-bit general pur- • Enables Transparent LAN configuration. pose I/O (GPIO) register. Services which, unlike POS • Provides 16-bit General solutions, do not require • Device power-up
Resumo do conteúdo contido na página número 7
2. Pinout 2.1 Pin Assignments GND DGND VDD DVDD NO CONNECT TX_SDCC_CLK TRSTB TX_SDCC_DATA TMS LOC_RX 5 TDO LOC_TX 115 TCK MDC TDI MDIO GPIO[0] P_TX_ER_M_RX_ER DGND 10 GND DGND DGND 110 GPIO[1] P_TX_EN_M_RX_DV GPIO[2] P_TXD_M_RXD[0] GPIO[3] P_TXD_M_RXD[1] GPIO[4] P_TXD_M_RXD[2] 15 GPIO[5] P_TXD_M_RXD[3] 105 GPIO[6] P_TX_CLK_M_RX_CLK GPIO[7] P_RX_ER_M_TX_ER DVDD VDD DGND 20 GND GND DGND 100 VDD DVDD RX_FRAME_IN P_RX_DV_M_TX_EN RX_SONETCLK P_RXD_M_TXD[0] RX_DATA[0] P_RXD_M_TXD[1] 25 RX_DATA[1] P_RX
Resumo do conteúdo contido na página número 8
2.2 Pin Descriptions Table 1. Line Side Interface Pins Description Signal name Pin # Type(I/O) Signal description RX_DATA[0] 25 I RECEIVE DATA: Byte-wide STS-3c data input stream. RX_DATA[1] 26 RX_DATA [7] is the MSB, and RX_DATA [0] the LSB. RX_DATA[2] 27 Data is sampled on the rising edge of RX_SONETCLK. RX_DATA[3] 28 RX_DATA[4] 29 RX_DATA[5] 32 RX_DATA[6] 33 RX_DATA[7] 34 RX_FRAME_IN 23 I RECEIVE FRAME INDICATOR: Frame position indication signal is active high and indicates the SONET frame
Resumo do conteúdo contido na página número 9
Signal name Pin # Type(I/O) Signal description TX_FRAME_SFP 125 O TRANSMIT FRAME POSITION OUTPUT INDICATOR: Frame position indication signal is active high and indicates the SONET frame position on the TX_DATA [7:0] bus. Updated on the rising edge of TX_SONETCLK. This signal is also used for the outer board to start sending the first bit (MSB) of the serial data E1, E2, F1, SDCC, and LDCC. TX_SONETCLK 133 I TRANSMIT SONET CLOCK: TX_SONETCLK is the transmit output clock to the line side, and pr
Resumo do conteúdo contido na página número 10
Signal name Pin # Type(I/O) Signal description MDIO 113 I/O MII management input/output serial data. When this interface is unused, connect this pin high. If HDMP-3001 is attached to a MAC via the mechanical interface specified in IEEE 802.3, clause 22.6, an external pull-up of 1.5 kohm ± 5% is required. MDC 114 I MII management clock, up to 2.5 MHz. When this interface is unused, connect this pin high. Table 3. Transport Overhead Pins Description Signal name Pin # Type(I/O) Signal description
Resumo do conteúdo contido na página número 11
Signal name Pin # Type(I/O) Signal description TX_E1_DATA 126 I TRANSMIT E1 DATA: Local orderwire channel data byte (E1) to be inserted by the HDMP-3001 into the outgoing SONET data stream. TX_E2_DATA 127 I TRANSMIT E2 DATA: Express orderwire channel data byte (E2) to be inserted by the HDMP-3001 into the outgoing SONET data stream. TX_F1_DATA 128 I TRANSMIT F1 DATA: Maintenance channel data byte (F1) to be inserted by the HDMP-3001 into the outgoing SONET data stream. TX_E1E2F1_CLK 129 O TRANSM
Resumo do conteúdo contido na página número 12
Table 4. Microprocessor Interface Pins Description Signal name Pin # Type(I/O) Signal description ADDR[0] 56 I ADDRESS BUS: Allows host microprocessor to perform ADDR[1] 57 register selection within the HDMP-3001. ADDR[2] 58 ADDR[3] 63 ADDR[4] 64 ADDR[5] 65 ADDR[6] 66 ADDR[7] 67 ADDR[8] 68 APS_INTB 83 O (O/D) APS INTERRUPT: Active-low output triggered by an APS event. APS_INTB is an open-drain output which is in a high impedance state when inactive. When used, this pin needs an external pull-up.
Resumo do conteúdo contido na página número 13
Signal name Pin # Type(I/O) Signal description INT 86 O (T/S) INTERRUPT: Configurable interrupt output. Refer to Table 18 for a detailed description of how INT is configured. In open-drain configurations, an external pull-up is required. In open-source configurations, an external pull-down is required. To prevent undesired interrupts before configuration is complete, microprocessors with an active-high interrupt pin should have a pull-down and those with an active-low interrupt pin, a pull-up. R
Resumo do conteúdo contido na página número 14
Table 6. Two-Wire EEPROM Interface Pins Description Signal name Pin # Type(I/O) Signal description SCL 92 I/O EEPROM bus clock. If no EEPROM is present, connect this pin to ground. Refer to EEPROM application notes for board pull-up requirements. SDA 89 I/O EEPROM bus data. If no EEPROM is present, connect this pin to ground. Refer to EEPROM app notes for board pull-up requirements. Table 7. Miscellaneous Pins Description Signal name Pin # Type(I/O) Signal description GPIO[0] 9 I/O (int. PU) GEN
Resumo do conteúdo contido na página número 15
Signal name Pin # Type(I/O) Signal description DGND 10, 11, 20, Driver GROUND: These pins should be connected to the I/O 40, 50, ground plane. 70, 80, 90, 100, 110, 120, 130, 140, 150, 160 VDD 2, 22, Logic POWER: These pins should be connected to the 1.8 V 42, 51, power supply for logic. 62, 82, 91, 102, 122, 131, 142 DVDD 19, 39, Driver POWER: These pins should be connected to the 3.3 V 59, 79, power supply for I/O. 99, 119, 139, 159 Note: I = Input, O = output, T/S = Tristateable output, O/D =
Resumo do conteúdo contido na página número 16
2.3 I/O Buffer Types This section lists the types of some particular I/Os used in the HDMP-3001 chip. Table 8. Buffer types Buffer Type I/O Name Comment O/D APS_INTB Need external P/U Output TS P_RXD_M_TXD[0] Controlled by the “Isolate MII” register bit Output P_RXD_M_TXD[1] P_RXD_M_TXD[2] P_RXD_M_TXD[3] P_RX_DV_M_TX_EN P_RX_ER_M_TX_ER INT See INT Pin Configuration Section RDYB Uses a T/S output buffer and logically drives high before output buffer is released or tristated Input TMS, TRSTB, TDI
Resumo do conteúdo contido na página número 17
3. Functional Description is in turn connected to an optical access to the internal chip regis- transceiver for interfacing to a ters through indirect addressing. 3.1 Introduction fiber. The Ethernet interface is a One of the vendor specific regis- The HDMP-3001 performs full- standard MII interface which op- ters is used to shadow the duplex mapping of Ethernet erates at 25 MHz (4-bit). Only 100 frequently polled master alarm frames into a SONET STS-3c / Mb/s full-duplex operation is sup- regis
Resumo do conteúdo contido na página número 18
3.2.5 SONET/SDH Interface 3.3.2 Software Reset 3.4 Bit Order This interface is 8 bits wide and Software resets are functionally runs at 19.44 MHz. The Serial equivalent to hardware resets. 3.4.1 GFP Mode SONET/SDH overhead channels There are two identical software The bit order for the MII nibbles are clocked in and out of the IC resets, one in the microprocessor through the HDMP-3001 chip is through low-speed serial ports. register map and one in the MII shown in Figure 4. The order in register
Resumo do conteúdo contido na página número 19
3.4.2 LAPS Mode clears the bit. If a clear occurs si- running counters are latched into In LAPS mode the FCS is calcu- multaneously with a parameter the hold registers and the running lated LSB first and the FCS sum is state change, the delta bit remains counters are cleared when a pulse transmitted in reversed bit order set. Delta bits are indicated by a occurs on LATCH_EVENT. within each byte. See Figure 6 and _D suffix. To prevent missing a count that Figure 7. occurs when latching occurs, a
Resumo do conteúdo contido na página número 20
Summary delta event bits provide The loopback modes are selected data is looped back to the line a consolidated view of the various by programming register bits in side transmit circuitry, from individual delta event bits, the register map. For details where it is sent out on the grouped either by function or please refer to the description of TX_DATA pins. SONET tributary. Summary delta register 0x001. events are therefore a function of The Ethernet loopback mode can the other delta events bits
