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CY7C1354C
CY7C1356C
9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL™ Architecture
[1]
Features Functional Description
• Pin-compatible and functionally equivalent to ZBT™ The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
• Supports 250-MHz bus operations with zero wait states
Latency™ (NoBL™) logic, respectively. They are designed to
— Available speed grades are 250, 200, and 166 MHz
support unlimited true back-to-back Read/Write
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CY7C1354C CY7C1356C Logic Block Diagram–CY7C1356C (512K x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S D P U E U ADV/LD A T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY WRITE DQs BWa E ARRAY S U CONTROL LOGIC G DRIVERS A F T DQPa I M E F BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Selec
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CY7C1354C CY7C1356C Pin Configurations 100-Pin TQFP Pinout DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V 4 V DDQ 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 71 SS V V DDQ DDQ 11 V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC 14 V NC 14 V 67 SS CY7C1354C 67 SS CY7C1356C V V DD 15 NC DD 15 NC 6
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CY7C1354C CY7C1356C Pin Configurations (continued) 119-Ball BGA Pinout CY7C1354C (256K × 36) 1 23 4 5 6 7 A V AA NC/18M A A V DDQ DDQ B NC/576M CE A ADV/LD ACE NC 2 3 C NC/1G A A V AA NC DD D DQ DQP V NC V DQP DQ c c SS SS b b DQ DQ V CE V DQ DQ E c c SS 1 SS b b F V DQ V V DQ V OE DDQ c SS SS b DDQ DQ DQ A DQ DQ G BW BW c c b b c b DQ DQ V DQ DQ H V c c SS WE b b SS V V NC V NC V V J DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ d d SS SS a a L DQ DQ NC DQ DQ BW BW d d a a d a M V DQ V V DQ V CEN D
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CY7C1354C CY7C1356C Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1354C (256K × 36) 1 2 3 4 567 89 10 11 A NC/576M A ADV/LD A A NC CE BW BW CE CEN 1 c b 3 B NC/1G A CE2 CLK WE OE NC/18M A NC BW BW d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS SS SS DDQ b DQ DQ V V V V V V V DQ DQ D c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ E c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ G c c DDQ DD SS SS SS DD
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CY7C1354C CY7C1356C Pin Definitions Pin Name I/O Type Pin Description A0, A1 Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of A Synchronous the CLK. BW ,BW , Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. a b BW ,BW , Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , c d a a a b b b BW controls DQ and DQP , BW controls DQ and DQP . c c c d d d WE Inp
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CY7C1354C CY7C1356C Pin Definitions (continued) Pin Name I/O Type Pin Description NC – No connects. This pin is not connected to the die. NC (18, 36, – These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 72, 144, 288, 288M, 576M and 1G densities. 576, 1G) ZZ Input- ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or
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CY7C1354C CY7C1356C Because the CY7C1354C and CY7C1356C are common I/O mode. While in this mode, data integrity is guaranteed. devices, data should not be driven into the device while the Accesses pending when entering the “sleep” mode are not outputs are active. The Output Enable (OE) can be deasserted considered valid nor is the completion of the operation HIGH before presenting data to the DQ guaranteed. The device must be deselected prior to entering and DQP (DQ /DQP for CY7C1354C and DQ
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CY7C1354C CY7C1356C [2, 3, 4, 5, 6, 7, 8] Truth Table Address Operation Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H - SLEEP MODE None X H X X X X X X Tri-State [2, 3, 4, 9] Partial Write Cycle Description Function (CY7C1354C) WE BW BW BW BW d c b a Read H X X X X Write –No bytes written L H H H H Write Byte a – (DQ and DQP
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CY7C1354C CY7C1356C Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1354C/CY7C1356C incorporates a serial boundary and is sampled on the rising edge of TCK. It is allowable to scan test access port (TAP) in the BGA package only. The leave this ball unconnected if the TAP is not used. The ball is TQFP package does not offer this functionality. This part pulled up internally, resulting in a logic HIGH level. oper
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CY7C1354C CY7C1356C TDI and TDO balls as shown in the Tap Controller Block through the instruction register through the TDI and TDO balls. Diagram. Upon power-up, the instruction register is loaded To execute the instruction once it is shifted in, the TAP with the IDCODE instruction. It is also loaded with the IDCODE controller needs to be moved into the Update-IR state. instruction if the controller is placed in a reset state as EXTEST described in the previous section. EXTEST is a mandatory
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CY7C1354C CY7C1356C PRELOAD allows an initial data pattern to be placed at the register is placed between the TDI and TDO balls. The latched parallel outputs of the boundary scan register cells advantage of the BYPASS instruction is that it shortens the prior to the selection of another boundary scan test operation. boundary scan path when multiple devices are connected together on a board. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, whi
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CY7C1354C CY7C1356C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Input timing refere
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CY7C1354C CY7C1356C Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the reg
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CY7C1354C CY7C1356C Boundary Scan Exit Order (256K × 36) Boundary Scan Exit Order (256K × 36) (continued) Bit # 119-ball ID 165-ball ID Bit # 119-ball ID 165-ball ID 1K4 B6 44 L2 K2 2H4 B7 45 K1 J2 3M4 A7 46 N2 M2 4F4 B8 47 N1 M1 5B4 A8 48 M2 L1 6G4 A9 49 L1 K1 7C3 B10 50 K2 J1 8B3 A10 51 Not Bonded Not Bonded (Preset to 1) (Preset to 1) 9D6 C11 52 H1 G2 10 H7 E10 53 G2 F2 11 G6 F10 54 E2 E2 12 E6 G10 55 D1 D2 13 D7 D10 56 H2 G1 14 E7 D11 57 G1 F1 15 F6 E11 58 F2 E1 16 G7 F11 59 E1 D1 17 H6 G
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CY7C1354C CY7C1356C Boundary Scan Exit Order (512K × 18) Boundary Scan Exit Order (512K × 18) (continued) Bit # 119-ball ID 165-ball ID Bit # 119-ball ID 165-ball ID 1K4 B6 39 T3 R3 2H4 B7 40 R2 P3 3M4 A7 41 R3 R1 4F4 B8 42 Not Bonded Not Bonded (Preset to 0) (Preset to 0) 5B4 A8 43 Not Bonded Not Bonded 6G4 A9 (Preset to 0) (Preset to 0) 7C3 B10 44 Not Bonded Not Bonded 8B3 A10 (Preset to 0) (Preset to 0) 9T2 A11 45 Not Bonded Not Bonded (Preset to 0) (Preset to 0) 10 Not Bonded Not Bonded (
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CY7C1354C CY7C1356C DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.......................................
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CY7C1354C CY7C1356C [16] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 55 5 pF IN A V = 3.3V V = 2.5V DD DDQ C Clock Input Capacitance 5 5 5 pF CLK C Input/Output Capacitance 5 7 7 pF I/O [16] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit Θ Thermal Resistance Test conditions follow standard 29.41 34.1 16.8 °C/W JA (Junction to Ambient) test meth
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CY7C1354C CY7C1356C [18, 19] Switching Characteristics Over the Operating Range –250 –200 –166 Parameter Description Min. Max. Min. Max. Min. Max. Unit [17] t V (typical) to the First Access Read or Write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5 6 ns CYC F Maximum Operating Frequency 250 200 166 MHz MAX t Clock HIGH 1.8 2.0 2.4 ns CH t Clock LOW 1.8 2.0 2.4 ns CL t OE LOW to Output Valid 2.8 3.2 3.5 ns EOV [20, 21, 22] t Clock to Low-Z 1.25 1.5 1.5 ns CLZ Output Times t Data Output Val
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CY7C1354C CY7C1356C Switching Waveforms [23, 24, 25] Read/Write Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BWX A1 A2 A4 ADDRESS A3 A5 A6 A7 t CO t t DS DH t t t t DOH CLZ OEV CHZ t t AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) n-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: 23. For this wavef
