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CY62147DV18
MoBL2™
4-Mb (256K x 16) Static RAM
mode reducing power consumption by more than 99% when
Features
deselected (CE HIGH or both BLE and BHE are HIGH). The
• Very high speed: 55 ns and 70 ns input/output pins (I/O through I/O ) are placed in a high-im-
0 15
pedance state when: deselected (CE HIGH), outputs are dis-
• Wide voltage range: 1.65V – 2.25V
abled (OE HIGH), both Byte High Enable and Byte Low Enable
• Pin-compatible with CY62147CV18
are disabled (BHE, BLE HIGH), or during a
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CY62147DV18 MoBL2™ [2, 3, 4] Pin Configuration FBGA (Top View) 1 2 4 5 3 6 A A A NC BLE OE 0 1 2 A A A I/O BHE CE I/O B 8 3 4 0 A C I/O I/O A I/O I/O 10 5 6 1 2 9 Vcc A V I/O A I/O SS D 11 17 7 3 Vss DNU A V I/O E CC I/O 12 16 4 F I/O I/O A A I/O I/O 13 14 15 14 5 6 A A G I/O NC WE I/O 13 15 12 7 A A A A NC NC 9 10 11 H 8 Notes: 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. 4. Pins H1, G2, and H6 in the BGA
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CY62147DV18 MoBL2™ Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current..................................................... > 200 mA Storage Temperature ................................–65°C to + 150°C Operating Range Ambient Temperature with Power Applied....
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CY62147DV18 MoBL2™ Electrical Characteristics Over the Operating Range (continued) CY62147DV18-55 CY62147DV18-70 [7] [7] Parameter Description Test Conditions Min. Typ. Max. Min. Typ. Max. Unit I Automatic CE CE > V −0.2V, V =1.95V L 0.5 12 0.5 12 µA SB1 CC CC(max) Power-Down V >V –0.2V, IN CC LL 8 8 Current — V <0.2V); f = f IN MAX V =2.25V L 0.5 18 0.5 18 CMOS Inputs (Address and Data CC(max) Only), f = 0 (OE, LL 12 12 WE, BHE and BLE) I Automatic CE CE > V – 0.2V, V =1.95V L 0.5 12 0.5 1
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CY62147DV18 MoBL2™ wqewqewq [9] Data Retention Waveform DATA RETENTION MODE V V CC(min) CC(min) V > 1.0 V V CC DR t t CDR R CE or BHE.BLE [10.] Switching Characteristics Over the Operating Range 55 ns 70 ns Parameter Description Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 55 70 ns RC t Address to Data Valid 55 70 ns AA t Data Hold from Address Change 10 10 ns OHA t CE LOW to Data Valid 55 70 ns ACE t OE LOW to Data Valid 25 35 ns DOE [11] t OE LOW to LOW Z 5 5 ns LZOE [11, 12] t OE
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CY62147DV18 MoBL2™ Switching Waveforms [14, 15] Read Cycle 1 (Address Transition Controlled) t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 16] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE BHE/BLE t LZOE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PU V I CC CC SUPPLY 50% 50% CURRENT I SB Notes: 14. The device is continuously selected. OE, CE = V , BHE and/or BLE = V . IL IL 15. WE is HIGH for r
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CY62147DV18 MoBL2™ Switching Waveforms (continued) [13, 17, 18] Write Cycle No. 1 (WE Controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t SD t HD DATA I/O NOTE19 DATA IN t HZOE [13, 17, 18] Write Cycle No. 2 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t SD t HD DATA I/O DATA IN NOTE 19 t HZOE Notes: 17. Data I/O is high impedance if OE = V . IH 18. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance stat
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CY62147DV18 MoBL2™ Switching Waveforms (continued) [18] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t t SD HD NOTE 19 DATAI/O DATA IN t LZWE t HZWE [18] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t HD t SD DATA I/O NOTE 19 DATA IN t LZWE Document #: 38-05343 Rev. *B Page 8 of 11 [+] Feedback
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CY62147DV18 MoBL2™ Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (I ) SB X X X H H High Z Deselect/Power-Down Standby (I ) SB L H L L L Data Out (I/O –I/O ) Read Active (I ) O 15 CC L H L H L Data Out (I/O –I/O ); Read (Lower byte only) Active (I ) O 7 CC I/O –I/O in High Z 8 15 L H L L H Data Out (I/O –I/O ); Read (Higher byte only) Active (I ) 8 15 CC I/O –I/O in High Z 0 7 L H H L L High Z Output Disabled Active (I ) CC L H H H L High
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CY62147DV18 MoBL2™ Package Diagram 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05343 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no re
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CY62147DV18 MoBL2™ Document History Page Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM Document Number: 38-05343 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 127482 06/17/03 HRT New Data Sheet *A 131009 11/26/03 CBD Changed From Advance to Preliminary *B 229908 See ECN AJU Changed From Preliminary to Final Added 70 ns speed bin Changed Vcc MAX spec from 2.20V to 2.25V Modified V spec on footnote #6 from V + 0.5V to V + 0.75V IH CC (MAX) CC (MAX) Changed I TYP
