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USER GUIDE
™
Tegra 200 Series Developer Board
Advance Information – Subject to Change
NVIDIA CONFIDENTIAL
January 2010 | DG-04927-001_v01
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Document Change History Version Date Description v01 JAN 22, 2010 Initial Release 2 Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL
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Tegra 200 Series Developer Board User Guide Table of Contents 1.0 INTRODUCTION .................................................................................................................................................................... 5 2.0 DEVELOPER BOARD OVERVIEW ........................................................................................................................................ 6 2.1 Feature List .................................................................
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Tegra 200 Series Developer Board User Guide 4.6 Display .............................................................................................................................................................................. 27 4.6.1 LCD Displays ............................................................................................................................................................................... 27 4.6.2 HDMI ......................................................
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Tegra 200 Series Developer Board User Guide 1.0 INTRODUCTION ™ The Smartbook Development System is an example of a development platform built around the Tegra 200 Series Developer Board. This example provides a starting point for continued development; it outlines a fairly typical Smartbook configuration based on the NVIDIA® Tegra™ 250 Computer-on-a-Chip. This document: Provides recommendations and integration guidelines for engineers to follow when designing a Smartbook or similar pro
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Tegra 200 Series Developer Board User Guide 2.0 DEVELOPER BOARD OVERVIEW 2.1 Feature List Applications Processor SD/SDIO and HSMMC NVIDIA Tegra 250, 23x23mm ,0.8mm pitch Standard SD/SDIO/MMC socket DRAM and Flash Memory USB and Ethernet 8, 128Mx8, DDR2 @ 333MHz SMSC LAN 9514 USB Hub and Ethernet TPS51116RGET DDR2 Buck Regulator - 3 USB Type A Host ports Hynix 8-bit NAND on board - USB for PCIE MiniCard Slot 2 Internal SD/MMC socket supports eMMC module - Ethernet RJ-45 Jack
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Tegra 200 Series Developer Board User Guide Figure 2. Tegra 200 Series Developer Board (Top View) VGA Conn (J12) HDMI LCD (J7) AC/DC Conn Jack (J18) Camera (J9) (J15) PCIE WiFi Ant Mini-B Mini- USB (J24) Card 0 (J27) SIM Card (J19) SD/MMC (J5) Battery PCIE Con Mini- (J14) PMU Card 1 (U7) (J27) Tegra T20 Ethernet (U4) Jack (J4) DDR2 USB Host (Rank 0) Port (J25) Dual USB Host Ports (J6) MMC VCORE (J20) Headphn Debug Internal Jack (J1) Conn SD/MMC (J10) (J26) Mic Jack (J2) Right Force Rec Sate
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Tegra 200 Series Developer Board User Guide 2.2 NVIDIA® Tegra™ 250 The NVIDIA Tegra 250 computer-on-a-chip is suited for handheld and mobile applications. It’s primary purpose is to control all system peripherals and provide computing power. Table 1 Features (Available / Used on Tegra 200 Series Developer Board) Dual-core ARM® Cortex-A9 MPCore™ processor CPU 32-bit 333MHz DDR2 SDRAM (to 1GB) External Memory Support 2 chip selects Dynamic voltage and frequency scaling Advanced
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Tegra 200 Series Developer Board User Guide 2.5 LCD Interface The Smartbook Development System routes an 18-bit parallel RGB interface from the Tegra 250 to a Texas Instruments SN75LVDS83B LVDS Transmitter which goes to an LVDS panel connector (J7). The connector is a Foxconn GS13307-11230- 7F. The controls available for the panel and backlight include: Panel power provided by main 3.3V Buck regulator and enabled by the Tegra 250 GPIO on LCD_PWR2 (EN_VDD_PNL) Backlight enable control
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Tegra 200 Series Developer Board User Guide of the USB ports are brought to standard Type A connectors (J6 – Dual host port connector and J25 – Single host port). The forth USB is routed to PCIe Mini-Card #1 (J28). 2.9 Storage There are two SD/MMC sockets on the Tegra 200 Series Developer Board. Both sockets support High Speed operation (52MHz for MMC, 50MHz for SD/SDIO) SD/MMC Socket 1 (J26) The J26 SD/MMC socket is a combination 8-bit MMC and 4-bit SD/MMC socket intended to be for i
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Tegra 200 Series Developer Board User Guide 2.12 User Interface Attach your USB keyboard and mouse to any of the available USB Type-A Host ports (J6, J25). 2.13 Miscellaneous Temperature Sensor On Semiconductor Model ADT7461AARMZ_RL7 0.25°C resolution/1°C accuracy (remote channel used) Interfaces to PWR_I2C Programmable over/under temperature limits Debug Options The Tegra 200 Series Developer Board provides development/debugging interfaces including JTAG, UART and Ethernet.
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Tegra 200 Series Developer Board User Guide 3.0 SATELLITE BOARD HEADERS Two dual row 50-pin expansion headers enable the ability to connect a satellite board to the Tegra 200 Series Developer Board and are used to extend developer board functionality. Figure 4. Example Satellite Board Block Diagram Tegra 200 Series Developer Additional Functionality Board (E1162) Wireless LEDs (WPAN, WWAN, WLAN) Modules Coin Cell PMU RESET LEDs (PWR, CHG, NUM, Button CAPS, SCROLL, RF) ONKEY ONKEY Butto
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Tegra 200 Series Developer Board User Guide 3.1 Satellite Board Headers All the interface connections between a satellite board and the Tegra 200 Series Developer Board are through two sets of Samtec FTS series 50-pin Micro Strips connectors. Table 2. Satellite Connectors Pinout Dir Pin # Signal Name Signal Name Pin # Dir Dir Pin # Signal Name Signal Name Pin # Dir In 1 KB_COL7 EC_KSO17 2 Out Out 1 LED_WPAN* VDD_CELL_RMT 2 In In 3 KB_COL6 EC_KSO16 4 Out Out 3 LED_WLAN* UART4
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Tegra 200 Series Developer Board User Guide 3.2 I2C Map The I2C interface can be used to connect a touch screen, touch pad and other devices. There are two options for the Touch devices. I2C versions of these devices (recommended) interface to the Tegra 250, while PS/2 versions connect to the EC controller. Table 3. Tegra 200 Series Developer Board I2C Map Domain Contrlr Pins Volt. Device ID / I2C Addr Location Tegra 250 Slave addr: VDDIO_VI I2C3 CAM_I2C_SCL/SDA 3.3V MEC1308 (I2C Mas
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Tegra 200 Series Developer Board User Guide 4.0 CONNECTION EXAMPLES 4.1 Power Figure 6. Tegra 250 Power Connection Example DG-04927-001_v01 Advance Information – Subject to Change 15 NVIDIA CONFIDENTIAL
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Tegra 200 Series Developer Board User Guide 4.1.1 Major Components 4.1.1.1 PMU The Tegra 200 Series Developer Board includes a multi-channel power management unit for embedded processors (TI TPS658621). Feature List Host Interface - I2C Control I/F - Core/CPU power request signals - 32.768KHz Clock - Reset input - Reset output RTC LDO - 1.0V-1.2V nominal voltage range with 25mV steps - Separate LDO for RTC domain allowing Deep Sleep mode support – the Tegra 250 lowest power mod
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Tegra 200 Series Developer Board User Guide 4.1.2 Power Supplies The Tegra 250 has 29 power rails (3 cores, 14 analog and 12 digital I/O). Depending on system design, many of the rails can share a power supply, and some are not needed for all designs. The example shown in Table 4 is based on the Smartbook Development System design and should be representative of these types of designs. This table mainly lists the supplies required by the Tegra 250. Others are required to support some o
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Tegra 200 Series Developer Board User Guide 4.1.3 Power Sequencing The Power solution, including the PMU and any external supplies/logic, must be able to meet the Tegra 250 power sequence requirements. These requirements are detailed in the Tegra 200 Series datasheet (Electrical, Mechanical and Thermal Specifications). Figure 7 shows the sequence used for the Smartbook Development System. Figure 7. Power-up Sequence Example VBAT (10.2-12.6V, 15V) VDD_5V0 (5V, DC/DC TPS51220A) VDD_3V3_SB
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Tegra 200 Series Developer Board User Guide 4.1.4 Bypass Capacitor Recommendations Table 5 lists the basic recommendations for bypass capacitors near the Tegra 250. In general, one 0.1uf per power pin (or group for cores) is desirable. These should be placed as close as possible to the respective power pins. In addition, for the higher power/higher frequency I/O rails one or more 4.7uf bulk capacitor is recommended and should be placed in the general area of the power and interface pins
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Tegra 200 Series Developer Board User Guide 4.2 Clocks The Tegra 250 has a large number of internal functional blocks supporting a broad range of interfaces. Each of these has its own clocking requirements. The RTC (Real Time Clock) and PMC (Power Management Controller) require a 32.768KHz clock, to be provided externally. In addition, a higher frequency reference clock (OSC) is required. This can come from a crystal or an external source, and feeds several integrated PLLs that provid
