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NEX-DDR3INTR-THIN
DDR3 800/1066MT/s Interposer
For use with the TLA7BB4 Logic Analyzer
Modules
Including these Software Support packages:
B_DDR3D_2D (Single/Dual/Quad Rank, single slot with Selective Clocking)
*B_DDR3D_2G (2 or 3 DIMM slots, two Rank @ 800MT/s)
*B_DDR3D_3A (2 DIMM slots, two Rank @ 1066MT/s)
* Optional Software
Copyright © 2007 Nexus Technology, Inc. All rights reserved.
Contents of this publication may not be reproduced in any form witho
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Product Warranty Due to wide variety of possible customer target implementations, this product has a 30 day acceptance period by the customer from the date of receipt. If the customer does not contact Nexus Technology within 30 days of the receipt of the product, it will be said that the customer has accepted the product. If the customer is not satisfied with this product, they may return it within 30 days for a refund. This Nexus Technology product has a warranty against defects in ma
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License Agreement In return for payment for this product, Nexus Technology grants the Customer a SINGLE user LICENSE in the software subject to the following: Use of the Software: - Customer may use the software on only one Tektronix mainframe logic analysis system at any given time - Customer may make copies or adaptations of the software (see Copies and Adaptations below for more information) - Customer may NOT reverse assemble or decompile the software Copies and Adaptati
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TABLE OF CONTENTS 1.0 OVERVIEW ........................................................................................................................... 9 1.1 General Information ............................................................................................................ 9 1.2 Software Package description..............................................................................................9 1.3 Eye size required ............................................
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B.3 TLA7BB4 Module to module skew.................................................................................. 75 APPENDIX C – 240-pin DDR3 DIMM Pinout ........................................................................... 76 APPENDIX D –Data Flow Through the Probes (coax cable to channel) .................................... 78 APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0.................................................. 80 APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot
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TABLE OF FIGURES Figure 1 – Drawing of Interposer with probes attached ............................................................... 15 Figure 2 – Samtec connector on the LEASH probe...................................................................... 16 Figure 3 – LEASH probe to NEX-PRB1X/2X connection .......................................................... 17 Figure 4 - Read Data Latency = CAS Latency + CAS Additive Latency + RDIMM (5+0+1) = 6 cycles) .............................
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TABLE OF TABLES Table 1 - B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping.................... 19 Table 2 - B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping.................... 25 Table 3 - B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping.................... 31 Table 4 - B_DDR3D_2D/_2G TLA MagniVu Channel Grouping .............................................. 45 Table 5 - B_DDR3D_3A TLA MagniVu Channel Grouping ..........................................
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DDR3THIN-MN-XXX 8 Doc. Rev. 1.11
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1.0 OVERVIEW 1.1 General Information The DDR3 Interposer Products are designed for ease of use. Interposers extra signal trace length, also an extra connector that might affect the quality of the system operation in some systems. • This Product is designed for capture of 1066MT/s or slower, and may only be used with the Tektronix TLA7BB4 acquisition modules. This product requires the use of the new NEX-PRB1X-T / PRB2X-T Low Profile Distributed probes available from Nexus
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NEX-DDR3INTR-THIN Interposer products. This support can be used with Single Rank and Dual Rank DIMMs. Note that this manual uses some terms generically. For instance, references to the TLA700/7000 apply to all suitable TLA700/7000 Logic Analyzers, or PCs being used to control the TLA. NEX-DDR3INTR-THIN refers to the B_DDR3D_2D/2G/3A software support packages. Appendix G has a silk-screened print of the NEX-DDR3INTR-THIN Logic Analyzer Interposer board. Referring to this drawing whil
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1.3 Eye size required The Eye size (stable data) required at the input resistor to the Nexus passive probes (NEX- PRB1X(-T) & NEX-PRB2X(-T)) is 330ps, and 0.2V. Capture accuracy may be affected if a stable eye can not meet this requirement. . The eye is a perfectly shaped diamond with each side equal distant from the center. 2.0 SOFTWARE INSTALLATION To Install the NEX-DDR3INTR-THIN software support place the B_DDR3D_XX Install CD in the CD drive of the TLA or the PC being us
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3.0 CONNECTING to the NEX-DDR3INTR-THIN INTERPOSER 3.1 General Care should be taken to support the weight of the acquisition probes so that the Logic Analyzer Interposer board and/or target socket are not damaged. 3.2 B_DDR3D_2D Support To acquire DDR3 Read and Write data at speeds up to 1066MT/s requires two merged TLA7BB4 136-channel, with 1.4G state option, acquisition cards and the use of the B_DDR3D_2D support software. The Master card will be in the lower numbered o
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TLA Master Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH (soldered-on coax cable) that is attached to “M_C” position on the Interposer. Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “M_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB1X-T “E” probe head to the NEX-PRBCOAX. Note the leads 9- 12 of the NEX-PRBCOAX must be connected to the second slots Chip Select lines (CS) near the second and third DIMM s
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TLA Slave1 Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB2X-T “C3/2” & “E3/2” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the Interposer. TLA Slave2 Connect the NEX-PRB1X-T A3/2 D3/2 probe head to DDR3 Interposer’s LEASH that is attached to “M_A3/2 A1/0” position on the second Interposer. Connect the NEX-PRB1X-T A1/0 D1/0 probe he
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3.5 Short “LEASH” probes The standard product includes 4 “LEASH” probes connected to this Interposer product. These short probes are soldered directly onto the interposer and interface the Interposer to the Passive probes that connect to the logic analyzer. These “LEASH” probes are to allow the user to easily install and remove the Interposer product in their system with out the added weight of the passive probe attached. There may be other probing options in the future. Contact Nexu
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The strain relief on the LEASH to NEXPRB1X/2X interface, while designed for bench handling, can be damaged by twisting the coax cables. Bends of over 45 degrees in this area should be avoided. The coax connection points, under any circumstances, are not to be bent. 3.5.1 Samtec connector on the LEASH probe pins Figure 2 – Samtec connector on the LEASH probe The LEASH probe connects to the NEX-PRB1X-T or NEX-PRB2X-T probe using two plastic nuts and screws, with a plastic sp
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3.5.2 LEASH probe to NEX-PRB1X/2X connection Probe tip on the NEX-PRB1X-T or Two each plastic NEX-PRB2X-T Spacers Screws & Nuts Interposer Hold each probe here together Transition board on the “LEASH” Cable end Figure 3 – LEASH probe to NEX-PRB1X/2X connection 3.5.3 Alternate use of NEX-PRB1X or NEX-PRB2X probes The NEX-PRB1X or NEX-PRB2X can be used in place of the “-T” probes but will have to be secured for long term connection by tie-wraps. DDR3THIN-MN-XXX 1
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3.6 Slot Numbering The Interposer must be installed in the furthest slot from the memory controller. For 1066MT/s support only the two furthest slots may be used. Slots are named as shown below: Slot naming for a three slot system Memory controller Slot C Slot B Slot A cS0-1# bS0-1# S0-3# cCLKE0-1 bCLKE0-1 CLKE0- (from NEX- (from NEX- PRBCOAX) PRBCOAX) If only one slot is used it must be the furthest slot from the memory controller. If two slots are used the
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Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin # Input Name Name Pin # Input RdA_DatHi RD_A_DQ63 234 S_A2:0 RdA_DatLo RD_A_DQ31 156 M_A0:6 (Hex) RD_A_DQ62 233 S_A2:1 (Hex) RD_A_DQ30 155 M_A0:3 RD_A_DQ61 228 S_A2:5 RD_A_DQ29 150 S_C2:0 RD_A_DQ60 227 S_CK0 RD_A_DQ28 149 S_C2:1 RD_A_DQ59 115 S_A2:2 RD_A_DQ27 37 M_A0:4 RD_A_DQ58 114 S_A2:3 RD_A_DQ26 36 M_A0:1 RD_A_DQ57 109 S_A2:7 RD_A_DQ25 31 S_C2:2 RD_A_DQ56 108 S_A3:0 RD_A_DQ24 30 S_C2:3 RD_A_DQ55 225 S_A3:2 RD
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Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin# Input Name Name Pin# Input RdB_DatHi RD_B_DQ63 234 S_A2:0^1 RdB_DatLo RD_B_DQ31 156 M_A0:6^1 (Hex) RD_B_DQ62 233 S_A2:1^1 (Hex) RD_B_DQ30 155 M_A0:3^1 RD_B_DQ61 228 S_A2:5^1 RD_B_DQ29 150 S_C2:0^1 RD_B_DQ60 227 S_CK0^1 RD_B_DQ28 149 S_C2:1^1 RD_B_DQ59 115 S_A2:2^1 RD_B_DQ27 37 M_A0:4^1 RD_B_DQ58 114 S_A2:3^1 RD_B_DQ26 36 M_A0:1^1 RD_B_DQ57 109 S_A2:7^1 RD_B_DQ25 31 S_C2:2^1 RD_B_DQ56 108 S_A3:0^1 RD_B_DQ24 30 S_C2:
