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Customer Notification
TM
VR4133
64-bit Microprocessor
Operating Precautions
µPD30133F3-266-GA3-A
Document No. TPS-HE-B-6009-4
Date Published: June 2004
NEC Electronics (Europe) GmbH
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DISCLAIMER The related documents in this customer notification may include preliminary versions. However, preliminary versions may not have been marked as such. The information in this customer notification is current as of its date of publication. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC’s data sheets or data books, etc., for the most up-to-date specifications of NEC PRODUCT(S). Not all PRODUCT(S) and/or types are a
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Table of Contents (A) Table of Operating Precautions .............................................................................................4 (B) Description of Operating Precautions...................................................................................5 (C) Valid Specification.................................................................................................................10 (D) Revision History ...............................................................
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TM Operating Precautions for VR4133 (A) Table of Operating Precautions µPD30133 No. Outline 1.2 1.3 Rev. 1.1 1.4 1.5 Note Rank I,K E P X L Simultaneous locking of cache lines with 1 the same index Reception of non IEEE802.3 conformant 2 packages 3 Register content in Ether0/1 blocks 4 Read access from external PCI master 5 Write access to external I/O area Branch delay slot of JAL(X) instruction in 6 MIPS16 mode 7 Disconnect at the end of PCI bu
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TM Operating Precautions for VR4133 (B) Description of Operating Precautions No. 1 Simultaneous locking of cache lines with the same index (Specification change notice) Details Simultaneous locking of two cache lines with the same index (i.e. in both cache ways) is prohibited. No. 2 Reception of non IEEE802.3 conformant packages (Specification change notice) Details In case of the reception of a non-IEEE802.3 conformant 18-Byte length Ethernet packet, the internal flow control logi
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TM Operating Precautions for VR4133 No. 5 Write access to external I/O area (Direction of usage) Details A write cycle to external I/O or Flash area after Note • a CPU read/write access to a BCU-managed registers • or a CPU I/O read after a bus hold • or a DMA I/O read after a bus hold • or a Flash memory read may drive the wrong write data. To avoid this situation, one of the following workarounds must be implemented: Note (1) execute a dummy register access to a non-BCU-managed
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TM Operating Precautions for VR4133 No. 7 Disconnect at the end of PCI burst cycle (Specification change notice) Details The last transfer of a PCI burst cycle is regarded as a disconnect cycle by VR4133, if STOP# and TRDY# are both asserted during the last-but-one data cycle, as shown in the following figure: unnecessary PCLK cycle A+0 D0 D1 A+8 D2 D3 A+12 D3 AD FRAME# IRDY# TRDY# STOP# mis-understan
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TM Operating Precautions for VR4133 No. 9 Ethernet: excessive data transfer into memory (Direction of usage) Details If two or more packets are received continuously, excessive data may be written at the end of a packet. The length of excessive data depends on the value of the DRBS0/1 bits of register RCV_CFGR0/1 (0x0f00 1618 / 0x0f00 1918) and becomes up to [burst length -1]. Therefore one of the following workarounds must be implemented: (1) Set up burst size as 1 word (4 bytes)
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TM Operating Precautions for VR4133 No. 11 Usage PCI and Ether/CEU/BCU/CSI (using DMA mode) simultaneously (Direction of usage) Details Using PCI and Ether / CEU / BCU / CSI (using DMA mode) simultaneously may occur a hang- up, if following 3 conditions are all satisfied: (1) CPU reads PCI bus or PCIU register (0x0f000cxx / 0x0f000dxx). (2) External PCI master reads or writes SDRAM connected to VR4133. (3) When using DMA between Ether/CEU/external I/O(ROM)/CSI and SDRAM. To avoid
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TM Operating Precautions for VR4133 (C) Valid Specification Item Date published Document No. Document Title 1 April 2004 U16551EJ2V0DS00 VR4133 Preliminary Data Sheet 2 February 2004 U16620EJ3V0UM00 VR4133 User Manual 10 Customer Notification
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TM Operating Precautions for VR4133 (D) Revision History Item Date published Document No. Comment st 1 October 2003 TPS-HE-B-6009-1 1 release 2 January 2004 TPS-HE-B-6009-2 Added item 8 to 12 3 May 2004 TPS-HE-B-6009-3 Modified item 10 4 June 2004 TPS-HE-B-6009-4 Added item 13 and 14 Customer Notification 11
