Streszczenie treści zawartej na stronie nr. 5
30 MHz AC Electrical Characteristics e g e a (See Notes 1 and 4 and Figures 1 thru 5 ). V 5V 10%, T 0§Cto 70§C for HPC467064. CC A Symbol and Formula Parameter Min Max Units Notes f CKI Operating Frequency 2 30 MHz C t e 1/f CKI Clock Period 33 500 ns C1 C t CKI High Time 22.5 ns CKIH t CKI Low Time 22.5 ns CKIL e t 2/f CPU Timing Cycle 66 ns C C e t t CPU Wait State Period 66 ns WAIT C t Delay of CK2 Rising Edge after CKI Falling Edge 0 55 ns (Note 2) DC1C2R t Delay of CK2 Falling Edge after CK
Streszczenie treści zawartej na stronie nr. 6
30 MHz AC Electrical Characteristics (Continued) e g e a (See Notes 1 and 4 and Figures 1 thru 5 ). V 5V 10%, T 0§Cto 70§C for HPC467064. (Continued) CC A Symbol and Formula Parameter Min Max Units Notes t e (/4 t b 5 ALE Falling Edge to RD Falling Edge 12 ns ARR C e a b t t WS 32 Data Input Valid after Address Output Valid 100 ns ACC C e a b t (/2 t WS 39 Data Input Valid after RD Falling Edge 60 ns RD C e a b t (/2 t WS 14 RD Pulse Width 85 ns RW C e b t */4 t 15 Hold of Data Input Valid after
Streszczenie treści zawartej na stronie nr. 7
CKI Input Signal Characteristics TL/DD/11046±4 Note: AC testing inputs are driven at V for logic ``1'' and V for a logic ``0''. Output timing measurements are made at V /2 for both logic ``1'' and logic ``0''. IH IL CC FIGURE 2. Input and Output for AC Tests Timing Waveforms TL/DD/11046±5 FIGURE 3. CK1, CK2, ALE Timing Diagram TL/DD/11046±6 FIGURE 4. Write Cycle 7
Streszczenie treści zawartej na stronie nr. 8
Timing Waveforms (Continued) TL/DD/11046±7 FIGURE 5. Read Cycle TL/DD/11046±8 FIGURE 6. Ready Mode Timing TL/DD/11046±9 FIGURE 7. Hold Mode Timing 8
Streszczenie treści zawartej na stronie nr. 9
Timing Waveforms (Continued) TL/DD/11046±10 FIGURE 8. MICROWIRE Setup/Hold Timing TL/DD/11046±11 FIGURE 9. UPI Read Timing TL/DD/11046±12 FIGURE 10. UPI Write Timing 9
Streszczenie treści zawartej na stronie nr. 10
Functional Modes of Operation There are two primary functional modes of operation for the The HPC167064 emulates the HPC16064 and HPC16083, HPC167064. except as described here. # EPROM Mode # The value of EXM is latched on the rising edge of RESET. Thus, the user may not switch from ROMed to Normal Running Mode # ROMless operation or vice-versa, without another EPROM MODE RESET pulse. In the EPROM mode, the HPC167064 is configured to ``ap- # The security logic can be used to control access to th
Streszczenie treści zawartej na stronie nr. 11
Functional Modes of Operation (Continued) Security Level 2 An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. This security level prevents programming of the on-chip The erasure time increases as the square of the distance. (If EPROM or the ECON registers thereby providing WRITE distance is doubled the erasure time increases by a factor of protection. Read accesses to the on-chip EPROM or ECON 4.) Lamps lose intensity as they age
Streszczenie treści zawartej na stronie nr. 12
Pin Descriptions The HPC167064 is available only in 68-pin LDCC package. POWER SUPPLY PINS V and CC1 I/O PORTS V Positive Power Supply CC2 Port A is a 16-bit bidirectional I/O port with a data direction GND Ground for On-Chip Logic register to enable each separate pin to be individually de- fined as an input or output. When accessing external memo- DGND Ground for Output Buffers ry, port A is used as the multiplexed address/data bus. Note: There are two electrically connected V pins on the chip,
Streszczenie treści zawartej na stronie nr. 13
Connection Diagram TL/DD/11046±17 Top View Order Number HPC167064, EL See NS Package Number EL68C PortsA&B The highly flexible A and B ports are similarly structured. A write operation to a port pin configured as an input causes The Port A (seeFigure 11), consists of a data register and a the value to be written into the data register, a read opera- direction register. Port B (seeFigures 12 thruFigure 14) has tion returns the value of the pin. Writing to port pins config- ured as outputs causes
Streszczenie treści zawartej na stronie nr. 14
PortsA&B (Continued) TL/DD/11046±20 FIGURE 12. Structure of Port B Pins B0, B1, B2, B5, B6 and B7 (Typical Pins) TL/DD/11046±21 FIGURE 13. Structure of Port B Pins B3, B4, B8, B9, B13 and B14 (Timer Synchronous Pins) 14
Streszczenie treści zawartej na stronie nr. 15
PortsA&B (Continued) TL/DD/11046±22 FIGURE 14. Structure of Port B Pins B10, B11, B12 and B15 (Pins with Bus Control Roles) Operating Modes To offer the user a variety of I/O and expanded memory DOG logic is engaged. A logic ``1'' in the EA bit enables options, the HPC167064 has four operating modes. The accesses to be made anywhere within the 64 kbytes ad- various modes of operation are determined by the state of dress range and the ``illegal address detection'' feature of both the EXM pin and
Streszczenie treści zawartej na stronie nr. 16
HPC167064 Operating Modes SINGLE CHIP NORMAL MODE In this mode, the HPC167064 functions as a self-contained microcomputer (see Figure 15 ) with all memory (RAM and EPROM) on-chip. It can address internal memory only, con- sisting of 16 kbytes of EPROM (C000 to FFFF) and 512 bytes of on-chip RAM and Registers (0000 to 02FF). The ``illegal address detection'' feature of the WATCHDOG is enabled in the Single-Chip Normal mode and a WATCH- DOG Output (WO) will occur if an attempt is made to access ad
Streszczenie treści zawartej na stronie nr. 17
HPC167064 Interrupts (Continued) TL/DD/11046±24 FIGURE 16. 8-Bit External Memory TL/DD/11046±25 FIGURE 17. 16-Bit External Memory 17
Streszczenie treści zawartej na stronie nr. 1
HPC167064/HPC467064 High-Performance microController
with a 16k UV Erasable CMOS EPROM
PRELIMINARY
August 1992
HPC167064/HPC467064 High-Performance
microController with a 16k UV Erasable CMOS EPROM
General Description
The HPC167064 is a member of the HPC family of High further current savings. The HPC167064 is available only in
Performance microControllers. Each member of the family 68-pin LDCC package.
has the same core CPU with a unique memory and I/O
configuration to suit specific application
Streszczenie treści zawartej na stronie nr. 2
Absolute Maximum Ratings b If Military/Aerospace specified devices are required, V with Respect to GND 0.5V to 7.0V CC please contact the National Semiconductor Sales a b All Other Pins (V 0.5V) to (GND 0.5V) CC Office/Distributors for availability and specifications. Note: Absolute maximum ratings indicate limits beyond Total Allowable Source or Sink Current 100 mA which damage to the device may occur. DC and AC electri- b a Storage Temperature Range 65 Cto 150 C cal specifications are not ensu
Streszczenie treści zawartej na stronie nr. 3
20 MHz AC Electrical Characteristics e g eb a e g (See Notes 1 and 4 andFigures 1 thru5 ). V 5V 5%*,T 55§Cto 125§C for HPC167064 and V 5V 10%, CC A CC e a T 0Cto 70 C for HPC467064 § § A Symbol and Formula Parameter Min Max Units Notes f CKI Operating Frequency 2 20 MHz C e t 1/f CKI Clock Period 50 500 ns C1 C t CKI High Time 22.5 ns CKIH t CKI Low Time 22.5 ns CKIL e t 2/f CPU Timing Cycle 100 ns C C e t t CPU Wait State Period 100 ns WAIT C t Delay of CK2 Rising Edge after CKI Falling Edge 0
Streszczenie treści zawartej na stronie nr. 4
20 MHz AC Electrical Characteristics (Continued) e g eb a e g (See Notes 1 and 4 andFigures 1 thru5 .) V 5V 5%*,T 55§Cto 125§C for HPC167064 and V 5V 10%, CC A CC e a T 0Cto 70 C for HPC467064 (Continued) A § § Symbol and Formula Parameter Min Max Units Notes t Delay from CKI Rising Edge to ALE Rising Edge 0 35 ns (Notes 1, 2) DC1ALER t Delay from CKI Rising Edge to ALE Falling Edge 0 35 ns (Notes 1, 2) DC1ALEF e a t (/4 t 20 Delay from CK2 Rising Edge to ALE Rising Edge 45 ns DC2ALER C e a t (/
Streszczenie treści zawartej na stronie nr. 18
HPC167064 Interrupts (Continued) TABLE II. Interrupts Vector Arbitration Interrupt Source Address Ranking FFFF:FFFE RESET 0 FFFD:FFFC Nonmaskable external on rising edge of I1 pin 1 FFFB:FFFA External interrupt on I2 pin 2 FFF9:FFF8 External interrupt on I3 pin 3 FFF7:FFF6 External interrupt on I4 pin 4 FFF5:FFF4 Overflow on internal timers 5 FFF3:FFF2 Internal on the UART transmit/receive complete or external on EXUI 6 FFF1:FFF0 External interrupt on EI pin 7 For the interrupts from the on-boar
Streszczenie treści zawartej na stronie nr. 19
19 TL/DD/11046±26 FIGURE 18. Block Diagram of Interrupt Logic
Streszczenie treści zawartej na stronie nr. 20
Timer Overview (Continued) (Clock Input/16) rate. It is used for WATCHDOG logic, high dividing the clock input. Timer T2 has additional capability of speed event capture, and to exit from the IDLE mode. Con- being clocked by the timer T3 underflow. This allows the sequently, it cannot be stopped or written to under software user to cascade timers T3 and T2 into a 32-bit timer/coun- control. Timer T0 permits precise measurements by means ter. The control register DIVBY programs the clock input to
