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TECHNICAL
MANUAL
LSI53C810A
PCI to SCSI I/O
Processor
Version 2.1
March 2001
®
S14067
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This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000168-00, First Edition (March 2
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Preface This book is the primary reference and technical manual for the LSI Logic LSI53C810A PCI to SCSI I/O Processor. It contains a complete functional description for the product and includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C810A PCI to SCSI I/O processor. It is intended for system designers and programmers who are using this device to design a SCSI port for PCI-based personal computers, workstations, or embedded
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• Chapter 6, Instruction Set of the I/O Processor, defines all of the SCSI SCRIPTS instructions that are supported by the LSI53C810A. • Chapter 7, Electrical Characteristics, contains the electrical characteristics and AC timings for the chip. • Appendix A, Register Summary, is a register summary. Related Publications For background please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way
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PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 SCSI SCRIPTS™ Processors Programming Guide, Order Number S14044.A Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.110
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vi Preface
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Contents Chapter 1 General Description ® 1.1 TolerANT Technology 1-2 1.2 LSI53C810A Benefits Summary 1-3 1.2.1 SCSI Performance 1-3 1.2.2 PCI Performance 1-4 1.2.3 Integration 1-4 1.2.4 Ease of Use 1-4 1.2.5 Flexibility 1-5 1.2.6 Reliability 1-5 1.2.7 Testability 1-6 Chapter 2 Functional Description 2.1 SCSI Core 2-1 2.1.1 DMA Core 2-2 2.2 SCRIPTS Processor 2-2 2.2.1 SDMS Software: The Total SCSI Solution 2-3 2.3 Prefetching SCRIPTS Instructions 2-3 2.3.1 Opcode Fetch Burst Capability 2-4 2.4 PCI
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2.7 Interrupt Handling 2-15 2.7.1 Polling and Hardware Interrupts 2-15 Chapter 3 PCI Functional Description 3.1 PCI Addressing 3-1 3.1.1 Configuration Space 3-1 3.1.2 PCI Bus Commands and Functions Supported 3-2 3.2 PCI Cache Mode 3-3 3.2.1 Support for PCI Cache Line Size Register 3-3 3.2.2 Selection of Cache Line Size 3-4 3.2.3 Alignment 3-4 3.2.4 Memory Read Multiple Command 3-7 3.2.5 Unsupported PCI Commands 3-8 3.3 Configuration Registers 3-9 Chapter 4 Signal Descriptions 4.1 PCI Bus Interface
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6.4.1 First Dword 6-13 6.4.2 Second Dword 6-22 6.5 Read/Write Instructions 6-23 6.5.1 First Dword 6-23 6.5.2 Second Dword 6-23 6.5.3 Read-Modify-Write Cycles 6-23 6.5.4 Move To/From SFBR Cycles 6-24 6.6 Transfer Control Instructions 6-27 6.6.1 First Dword 6-27 6.6.2 Second Dword 6-35 6.7 Memory Move Instructions 6-36 6.7.1 First Dword 6-38 6.7.2 Second Dword 6-38 6.7.3 Third Dword 6-38 6.7.4 Read/Write System Memory from a SCRIPTS Instruction 6-39 6.8 Load and Store Instructions 6-39 6.8.1 First
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Figures 1.1 LSI53C810A System Diagram 1-7 1.2 LSI53C810A Chip Block Diagram 1-8 2.1 DMA FIFO Sections 2-8 2.2 LSI53C810A Host Interface Data Paths 2-10 2.3 Active or Regulated Termination 2-12 2.4 Determining the Synchronous Transfer Rate 2-15 4.1 LSI53C810A Pin Diagram 4-2 4.2 Functional Signal Grouping 4-4 5.1 Register Address Map 5-2 6.1 SCRIPTS Overview 6-5 6.2 Block Move Instruction Register 6-8 6.3 I/O Instruction Register 6-16 6.4 Read/Write Register Instruction 6-25 6.5 Transfer Control
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7.21 Target Asynchronous Send 7-29 7.22 Target Asynchronous Receive 7-30 7.23 Initiator and Target Synchronous Transfers 7-30 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) 7-34 Tables 2.1 Bits Used for Parity Control and Observation 2-6 2.2 SCSI Parity Control 2-7 2.3 SCSI Parity Errors and Interrupts 2-7 3.1 PCI Bus Commands and Encoding Types 3-9 3.2 PCI Configuration Register Map 3-10 4.1 Power and Ground Signals 4-3 4.2 System Signals 4-5 4.3 Address and Data Signals 4-6 4.4 Interfa
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7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ 7-5 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/ 7-6 7.12 TolerANT Technology Electrical Characteristics 7-7 7.13 Clock Timing 7-10 7.14 Reset Input Timing 7-11 7.15 Interrupt Output 7-11 7.16 PCI Timing 7-26 7.17 Initiator Asynchronous Send (5 Mbytes/s) 7-27 7.18 Initiator Asynchronous Receive (5 Mbytes/s) 7-28 7.19 Target Asynchronous Send (5 Mbytes/s) 7-29 7.20 Target Asynchronous Rece
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Chapter 1 General Description Chapter 1 is divided into the following sections: ® • Section 1.1, “TolerANT Technology” • Section 1.2, “LSI53C810A Benefits Summary” The LSI53C810A PCI to SCSI I/O processor brings high-performance I/O solutions to host adapter, workstation, and general computer designs, making it easy to add SCSI to any PCI system. The LSI53C810A is a pin-for-pin replacement for the LSI53C810 PCI to SCSI I/O processor. It performs fast SCSI transfers in Single-Ended (SE) mode, and
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Software development tools are available to developers who use the SCSI SCRIPTS language to create customized SCSI software applications. The LSI53C810A allows easy firmware upgrades and is supported by advanced SCRIPTS commands. ® 1.1 TolerANT Technology The LSI53C810A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather
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1.2 LSI53C810A Benefits Summary This section provides an overview of the LSI53C810A features and benefits. It contains these topics: • SCSI Performance • PCI Performance • Integration • Ease of Use • Flexibility • Reliability • Testability 1.2.1 SCSI Performance To improve SCSI performance, the LSI53C810A: • Complies with PCI 2.1 specification • Supports variable block size and scatter/gather data transfers • Minimizes SCSI I/O start latency • Performs complex bus sequences without interrupts, incl
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1.2.2 PCI Performance To improve PCI performance, the LSI53C810A: • Bursts 2, 4, 8, or 16 Dwords across PCI bus with 80-byte DMA FIFO • Prefetches up to 8 Dwords of SCRIPTS instructions • Supports 32-bit word data bursts with variable burst lengths. • Bursts SCRIPTS opcode fetches across the PCI bus • Performs zero wait-state bus master data bursts faster than 110 Mbytes/s (@ 33 MHz) • Supports PCI Cache Line Size register 1.2.3 Integration Features of the LSI53C810A which ease integration inclu
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• Three programmable SCSI timers: Select/Reselect, Handshake-to- Handshake, and General Purpose. The time-out period is programmable from 100 μs to greater than 1.6 seconds • SDMS software for complete PC-based operating system support • Support for relative jump • New SCSI Selected As ID (SSAID) bits for use when responding with multiple IDs 1.2.5 Flexibility The LSI53C810A provides: • High level programming interface (SCSI SCRIPTS) • Support for execution of tailored SCSI sequences from main s
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• Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certification) • Latch-up protection greater than 150 mA • Voltage feed-through protection (minimum leakage current through SCSI pads) • High proportion (> 25%) of pins power and ground • Power and ground isolation of I/O pads and internal chip logic • TolerANT technology, which provides: – Active negation of SCSI Data, Parity, Request, and Acknowledge signals for improved fast SCSI transfer rates. – Input signal fi
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Figure 1.1 LSI53C810A System Diagram SCSI Connection SCSI Term Connection V V DD SS SCSI Bus PCI Bus LSI53C810A Peripheral 40 MHz Oscillator or Optional Internal Bulkhead Connection to PCI Bus Clock CPU Baseboard CPU Box LSI53C810A Benefits Summary 1-7
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Figure 1.2 LSI53C810A Chip Block Diagram PCI PCI Master and Slave Control Block Data Configuration Operating SCSI FIFO Registers Registers SCRIPTS 80 Bytes SCSI FIFO and SCSI Control Block TolerANT Technology Drivers and Receivers SE SCSI Bus 1-8 General Description
