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LXD9785 PQFP Demo Board with
FPGA for SS-SMII (Fiber)-to-MII
Conversion
Development Kit Manual
January 2002
Order Number: 249323-003
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® Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose,
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Contents Contents 1.0 General Description.........................................................................................................................7 1.1 Features................................................................................................................................7 2.0 Introduction......................................................................................................................................9 2.1 Overview..............................
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Contents Tables 1 Quick-Start Jumper Settings....................................................................................................... 12 2 Quick-Start Switch Settings ........................................................................................................13 3 Global Configuration Settings (Switch S5) .................................................................................14 4 Global Configuration Settings (Switch S8) .......................................
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Contents Revision History Date Revision Page Description All Replaced LXT9785 with LXT9785/9785E globally January 2002 003 Added new section 4.5 Expended Temperature Operation with the 16 LXT9785HE. 11 Replaced LXD9785 demo board graphic with A2 version. 12 Quick Start Jumper Settings table: Added JP15 and JP16. Quick Start Switch Settings table: - Removed TxSLEW (S5-1:2) - Renumbered remaining switches 13 - Replaced MDIX with Section and new configuration. - Removed “Auto-Negotiation, 10/” un
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 1.0 General Description The LXD9785 PQFP MII Demo Board is an eight-port 100 Mbps Fast Ethernet Media Access Unit (MAU) that provides a working platform for evaluation of the LXT9785/9785E Fast Ethernet Octal Transceiver. All eight network ports provide a fiber interface for a 100BASE-FX connection. The Demo Board allows system designers to test 100 Mbps Fiber link performance and register functionality using a standard
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Figure 1. LXD9785 PQFP MII Demo Board Port 0 MII Port 1 MII Port 2 MII Port 3 MII Port 4 MII Port 5 MII Port 6 MII Port 7 MII Header Header Header Header Header Header Header Header FPGA FPGA SS-SMII to MII Converter and SS-SMII to MII Converter and Inter Frame Status Output Connector Inter Frame Status Output Connector RJ-11 Config Logic Inter Frame Switches & Jumpers Status LEDs LXT9785/9785E REFCLK Clocks and Clock Distr
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 2.0 Introduction 2.1 Overview This document describes typical hardware set-up procedures for the LXD9785 PQFP MII Demo Board. To begin immediate operation, a “Quick-Start Checklist” on page 12 supports 100BASE- FX operation. Hardware switches and jumpers allow the designer access to all hardware configuration options. Each option is outlined in the “Optional Configurations” on page 14. The Demo Board provides two sets of
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 2.4 Typical Setup Figure 2 shows a typical test setup for standard operation of the LXD9785/9785E PQFP MII Demo Board. The Demo Board plugs into a SmartBits Advanced Multi-port Performance Test Box via eight standard 40-pin MII cables (not included on the board). Eight external NIC cards directly connect to the SmartBits test box and plug into the Demo Board through fiber-module connectors. Each port’s operation speed is
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Figure 3. LXD9785/9785E SS-SMII Fiber Demo Board Development Kit Manual 11 Document #: 249323 Revision #: 003 Rev. Date: January 24, 2002
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 3.0 Quick-Start Checklist Use this quick-start procedure for easy setup of the LXD9785 PQFP MII Demo Board. This procedure sets all ports to the default condition (100 Mbps and full-duplex capabilities). 1. Set the jumpers in accordance with Table 1. 2. Set switches S1, S5, and S8 in accordance with Table 2. 3. Connect the eight Demo Board MII ports to the SmartBits test box via MII connector/cables. Male-to- male conne
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Table 2. Quick-Start Switch Settings Switch / Label Setting Configuration Switch S1 S1-1 / ADD_0 0 S1-2 / ADD_1 0 S1-3 / ADD_2 0 Sets PHY MDIO base address to 00000. S1-4 / ADD_3 0 S1-5 / ADD_4 0 Switch S5 S5-1 / PAUSE 0 Disables Pause function. S5-2 / PWRDWN 0 Disables Power-Down function. S5-3 / MDDIS 0 Enables MDIO channel. Switch S8 S8-1 / ModeSel 0 0 Switch settings for SS-SMII mode. S8-2 / ModeSel 1 1 S8-3 /Section 0 E
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 4.0 Optional Configurations 4.1 Global Operating Configurations Switch S5 and S8 configure operating characteristics on all ports of the LXD9875 Demo Board. Each switch can be set manually by toggling the switch either to 1 or 0. Set switches S5 and S8 to the desired configuration according to Table 3 and Table 4 respectively. Table 3. Global Configuration Settings (Switch S5) Switch / Label Description Pause - Enable Paus
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Table 5. PHY Address Configuration Settings (Switch S1) Jumper / Label Description S1-1 / ADD_0 Address <4:0> - Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. S1-2 / ADD_1 Switch “0” sets address bit to 0. S1-3 / ADD_2 Switch “1” sets address bit to 10. Note: To make all ports accessible within the 0 - 31 PHY address range, DO NOT S1-4 / ADD_3 select a bas
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 4.4 JTAG Test Signals The boundary scan test port is accessed via JP3 for board- level testing. The JTAG test signal descriptions are shown in Table 7. The BSDL file for the LXT9785/9785E is available on the Intel web site at http://developer.intel.com/design/network/. Table 7. JTAG Test Signal Descriptions Jumper Pin# Symbol Description 1TRST# Test Reset. Input sourced by ATE 3TCK Test Clock. Input sourced by ATE. 5TMS Te
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion 5.0 LEDs 5.1 Direct Drive LEDs The LXD9785 PQFP MII Demo Board provides three programmable LED drivers per port (D4 - D28). Each LED can display one of several available status conditions as selected by the LED Configuration Register (Address 20) shown in Table 8. . Table 8. Direct Drive LED Configuration Settings (Register 20) LED Bits Program Description Bits LED1 LED2 LED3 0000 Indicates 100 Mbps operation. (Default f
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Table 9. LED Pulse Stretch Settings (Register 20) Bit Name Description Type Default 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 20.3:2 LEDFREQ R/W 00 10 = Stretch LED events to 100 ms. 11 = Reserved. PULSE- 0 = Disable pulse stretching of all LEDs. 20.1 R/W 1 STRETCH 1 = Enable pulse stretching of all LEDs. 5.2 Inter Frame Status LEDs By using the conversion FPGAs, the Inter Frame Status information f
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Figure 5. Control 20 Development Kit Manual Document #: 249323 Revision #: 003 Rev. Date: January 24, 2002 A B C D E VCCIO VCCIO 14 REF_CLK_0 REF_CLK_0 U1I R6 4.7K 14 REF_CLK_1 REF_CLK_1 83 AMDIX_EN AMDIX_EN S8 MDC0 63 MDC0 MDC1 24 177 MODESEL_0 1 12 MDC1 MODESEL_0 MDIO0 MODESEL_1 64 178 2 11 MDIO0 MODESEL_1 R14 R15 R25 R16 R17 R10 MDIO1 SECTION 25 176 3 10 MDIO1 SECTION 59 MDIX 4 9 JP1 MDIX VCCIO 4.7K 4.7K 4.7K 4.7K 4.7K 4.
